DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 33-38 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected claims, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 6/22/2026.
Applicant canceled non-elected claims 33-38 without traverse.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 15, reciting “- - (hereinafter, referred to as a second vertical hole) - - “ is not clear since a first vertical hole isn’t introduced in claim 15 and also “( - -)” isn’t allowed in claim. Please delete “(hereinafter, referred to as a second vertical hole)” or change to a second vertical hole with introducing a first vertical hole.
Allowable Subject Matter
Claims 1-14 & 16-31 are allowed over the prior art.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
The prior art does not teach or render not obvious “- - an insulating material by filling the empty spaces on both sides of the at least one pattern portion with the insulating material - - forming an epitaxial material plug filling the first vertical hole from the substrate by using an epitaxial growth method; forming a first etched portion spaced apart from the epitaxial material plug in the structure; forming a horizontal hole extending in the first direction by removing the first sacrificial layer pattern exposed by the first etched portion; forming an epitaxial channel material layer filling the horizontal hole from a side surface of the epitaxial material plug by using an epitaxial growth method; forming an empty region around the epitaxial material plug and the epitaxial channel material layer by removing the first and second insulating layers and the insulating material from the structure - -forming a filling insulating layer filling the empty region on the gate insulating material layer; forming a second vertical hole in a region corresponding to the first vertical hole in the structure where the gate insulating material layer and the filling insulating layer are formed; exposing the gate insulating material layer by removing the filling insulating layer from a transistor formation region around the second vertical hole of the structure; defining a transistor including a word line by forming the word line surrounding an exposed portion of the gate insulating material layer in the transistor formation region; forming a bit line connected to one end of the epitaxial channel material layer in a region corresponding to the second vertical hole in the transistor formation region; and removing the epitaxial channel material layer and the gate insulating material layer from a capacitor formation region adjacent to the transistor formation region of the structure, and forming a capacitor connected to the other end of the epitaxial channel material layer of the transistor.” with combination of other claim limitations in claim 1.
Also, the prior art does not teach or render not obvious “- - forming an epitaxial material plug filling the first etched portion from the substrate by using an epitaxial growth method; forming a second etched portion spaced apart from the epitaxial material plug in the stack; forming a horizontal space by removing the first sacrificial layer exposed by the second etched portion - - forming a structure including the epitaxial plug pattern, the epitaxial channel pattern, the gate insulating material layer, and an filling insulating layer by forming the filling insulating layer filling a space surrounding the epitaxial plug pattern and the epitaxial channel pattern on the gate insulating material layer; forming a first vertical hole exposing the epitaxial channel pattern in a region corresponding to the bit line formation planned region; exposing the gate insulating material layer by removing the filling insulating layer from a transistor formation region around the first vertical hole of the structure - -removing the epitaxial channel pattern and the gate insulating material layer from a capacitor formation region adjacent to the transistor formation region of the structure, and forming a capacitor connected to the other end of the epitaxial channel pattern of the transistor.” with combination of other claim limitations in claim 16.
Furthermore, the prior art does not teach or render not obvious “- -removing the epitaxial plug pattern and forming a first vertical hole exposing the epitaxial channel pattern by etching a bit line formation planned region in the structure; exposing the gate insulating material layer by removing the filling insulating layer from a transistor formation region around the first vertical hole of the structure; forming a word line surrounding an exposed portion of the gate insulating material layer in the transistor formation - - removing the epitaxial channel pattern and the gate insulating material layer from a capacitor formation region adjacent to the transistor formation region of the structure, and forming a capacitor connected to the other end of the epitaxial channel pattern of the transistor.” with combination of other claim limitations in claim 31.
Claim 16 is allowable if applicant overcomes the 112 2nd rejection.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SU C KIM/Primary Examiner, Art Unit 2899
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