Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The amendment made to the title of the invention in the response filed on July 8, 2026 is accepted by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the common contact is a single continuous conductive structure and functions as both the source contact and the drain contact,” on page 3 lines 21-22. This limitation renders the claim indefinite because it is unclear how the common contact is located between the drain contact and the source contact, as previously recited in claim 1 on page 3 lines 9-10, and also functions as the drain contact and the source contact that the common contact is located between. For examination purposes, this limitation will be interpreted as reciting the common contact is a single continuous conductive structure and functions as both a second source contact and a second drain contact.
Claims 2-13 are also rejected for containing the same limitation because claims 2-13 depend from claim 1.
Claim 14 recites the limitation “wherein the common contact is a single continuous conductive structure and functions as both the source contact and the drain contact,” on page 5 lines 21-23. This limitation renders the claim indefinite because it is unclear how the common contact is formed between the drain contact and the source contact, as previously recited in claim 14 on page 5 lines 20-21, and also functions as the drain contact and the source contact that the common contact is formed between. For examination purposes, this limitation will be interpreted as reciting wherein the common contact is a single continuous conductive structure and functions as both a second source contact and a second drain contact.
Claims 15-20 are also rejected for containing the same limitation because claims 15-20 depend from claim 14.
Claim 21 recites the limitation “the common contact is a single continuous conductive structure and functions as both the source contact and the drain contact,” on page 7 lines 20-21. This limitation renders the claim indefinite because it is unclear how the common contact is located between the drain contact and the source contact, as previously recited in claim 21 on page 7 lines 11-12, and also functions as the drain contact and the source contact that the common contact is located between. For examination purposes, this limitation will be interpreted as reciting the common contact is a single continuous conductive structure and functions as both a second source contact and a second drain contact.
Claims 22-27 are also rejected for containing the same limitation because claims 22-27 depend from claim 21.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lyu et al. (“A GaN Power Integration Platform Based on Engineered Bulk Si Substrate with Eliminated Crosstalk between High-Side and Low-Side HEMTs”).
Regarding Claim 21:
Lyu discloses a semiconductor device, comprising:
a substrate (engineered bulk silicon substrate, See fig. 1 and Section I paragraph 3);
a first nitride semiconductor layer (undoped GaN channel layer, See Section II, subsection A) on the substrate;
a second nitride semiconductor layer (AlGaN layer, See fig. 1 and Section II, subsection A) on the first nitride semiconductor layer and having a band gap greater than a band gap of the first nitride semiconductor layer (The AlGaN has a wider band gap than the undoped GaN channel layer to form a 2D electron gas in the undoped GaN channel. The examiner notes the characteristics of the 2D electron gas are shown in table 1.);
a drain contact (right drain contact, See fig. 1) on the second nitride semiconductor layer;
a source contact (left source contact, See fig. 1) on the second nitride semiconductor layer;
a common contact (structure formed by the left drain contact, the right source contact, and the metal layer connecting the left drain contact and the right source contact, See fig. 1) on the second nitride semiconductor layer and between the drain contact and the source contact;
a first gate structure (right gate, See fig. 1) on the second nitride semiconductor layer and between the drain contact and the common contact; and
a second gate structure (left gate, See fig. 1) on the second nitride semiconductor layer and between the common contact and the source contact,
wherein the source contact is electrically connected to the substrate through a conductive via (the left source contact is electrically connected to the P+ Si doped layer of the engineered bulk silicon substate through a metal layer and a left contact to P+ Si doped layer of the engineered bulk silicon substrate, See fig. 1), and a shortest distance between the first gate structure and the common contact is smaller than a shortest distance between the second gate structure and the common contact (the distance between the right gate and the source contact of the structure formed by the left drain contact, the right source contact, and the metal layer connecting the left drain contact and the right source contact is 2µm and the distance between the left gate and the drain contact of the structure formed by the left drain contact, the right source contact, and the metal layer connecting the left drain contact and the right source contact is 5µm, See Section III, subsection A), and the common contact is a single continuous conductive structure and functions as both the source contact and the drain contact (the structure formed by the left drain contact, the right source contact, and the metal layer is continuous because there are no breaks or gaps in the structure and the structure functions as both a second source contact and a second drain contact because the structure contains both a source contact and a drain contact).
Regarding Claim 22:
Lyu discloses wherein the shortest distance between the first gate structure and the common contact is smaller than a shortest distance between the first gate structure and the drain contact (the distance between the right gate and the source contact of the structure formed by the left drain contact, the right source contact, and the metal layer connecting the left drain contact, the right source contact is 2µm and the distance between the right gate and the right drain is 5µm, See Section III, subsection A).
Regarding Claim 23:
Lyu discloses wherein the shortest distance between the second gate structure and the common contact is greater than a shortest distance between the second gate structure and the source contact (the distance between the left gate and the drain contact of the structure formed by the left drain contact, the right source contact, and the metal layer connecting the left drain contact, the right source contact is 5µm and the distance between the left gate and the left source is 2µm, See Section III, subsection A).
Regarding Claim 24:
Lyu discloses the above stated semiconductor device a dielectric layer (dielectric material layer on the AlGaN layer, See fig. 1 and Section II, subsection. The examiner notes that the layer on the AlGaN layer is understood to be a dielectric material layer because the same material fills the trenches shown in figure 1.) on the second nitride semiconductor layer, wherein the dielectric layer covers a portion of a lateral surface of the conductive via, the lateral surface facing the source contact or the drain contact (the dielectric material covers a portion of the right lateral surface of the left contact to P+ Si doped layer of engineered bulk silicon substrate that faces the left source contact and the right drain contact, See fig. 1).
Regarding Claim 25:
Lyu discloses wherein a portion of the dielectric layer is between the source contact and the conductive via (the portion of the dielectric material layer between the source contact and the left contact to P+ Si doped layer of engineered bulk silicon substrate, See fig. 1).
Regarding Claim 26:
Lyu discloses a conductive wire (metal layer on the left source contact and left contact to P+ Si doped layer of engineered bulk silicon substrate, See fig. 1. The examiner notes that the light grey layer on the left source contact is understood to be metal based color coding of the layers in figure 1. The examiner notes that the light grey layer on the backside engineered bulk silicon substrate is described as a backside metal in the caption to figure 1.) on the source contact, wherein the conductive via is connected to the conductive wire (See fig. 1).
Regarding Claim 27:
Lyu discloses wherein the conductive wire has a lower surface facing the substrate and extending beyond the source contact and the conductive via is connected to the lower surface of the conductive wire (the metal layer on the left source contact and left contact to P+ Si doped layer of engineered bulk silicon substrate has lower surface facing the engineered bulk silicon substrate that extends beyond the source contact and the left contact to P+ Si doped layer of engineered bulk silicon substrate is connected to this metal layer, See fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lyu et al. (“A GaN Power Integration Platform Based on Engineered Bulk Si Substrate with Eliminated Crosstalk between High-Side and Low-Side HEMTs”) in view of Jeon et al. (US 10,749,019).
Regarding Claim 1:
Lyu discloses a semiconductor device, comprising:
a substrate (engineered bulk silicon substrate, See fig. 1 and Section I paragraph 3);
a first nitride semiconductor layer (undoped GaN channel layer, See Section II, subsection A) on the substrate;
a second nitride semiconductor layer (AlGaN layer, See fig. 1 and Section II, subsection A) on the first nitride semiconductor layer and having a band gap greater than a band gap of the first nitride semiconductor layer (The AlGaN has a wider band gap than the undoped GaN channel layer to form a 2D electron gas in the undoped GaN channel. The examiner notes the characteristics of the 2D electron gas are shown in table 1.);
a drain contact (right drain contact, See fig. 1) on the second nitride semiconductor layer;
a source contact (left source contact, See fig. 1) on the second nitride semiconductor layer;
a common contact (structure formed by the left drain contact, the right source contact, and the metal layer connecting the left drain contact and the right source contact, See fig. 1) on the second nitride semiconductor layer and between the drain contact and the source contact;
a first gate structure (right gate, See fig. 1) on the second nitride semiconductor layer and between the drain contact and the common contact;
a second gate structure (left gate, See fig. 1) on the second nitride semiconductor layer and between the common contact and the source contact;
a conductive wire (metal layer on the left source contact and left contact to P+ Si doped layer of the engineered bulk silicon substrate, See fig. 1. The examiner notes that the light grey layer on the left source contact is understood to be metal based color coding of the layers in figure 1. The examiner notes that the light grey layer on the backside engineered bulk silicon substrate is described as a backside metal in the caption to figure 1.) on the source contact;
a dielectric layer (dielectric material layer on the AlGaN layer, See fig. 1 and Section II, subsection B. The examiner notes that the layer on the AlGaN layer is understood to be a dielectric material layer because the same material fills the trenches shown in figure 1.) on the second nitride semiconductor layer; and
a conductive the via (left contact to P+ Si doped layer of the engineered bulk silicon substrate, See fig. 1, Section I paragraph 2 and Section II subsection B) connected to the conductive wire,
wherein the conductive via extends through a portion of the dielectric layer, the second nitride semiconductor layer, and the first nitride semiconductor layer to the substrate (the left contact extends through the dielectric material layer, the AlGaN layer, the undoped GaN channel layer to the P+ Si doped layer of the engineered bulk silicon substrate, See fig. 1) and the common contact is a single continuous conductive structure and functions as both the source contact and the drain contact (the structure formed by the left drain contact, the right source contact, and the metal layer is continuous because there are no breaks or gaps in the structure and the structure functions as both a second source contact and a second drain contact because the structure contains both a source contact and a drain contact).
Lyu does not disclose the dielectric layer covering a portion of a lateral surface of the conductive wire.
Jeon discloses the dielectric layer covering a portion of a lateral surface of the conductive wire (insulating layer covering a portion of a lateral surface a gate electrode on a barrier layer, See fig. 7, ref. nos. 508, 524, 700, and col. 8 lines 1-19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lyu to include the dielectric layer covering a portion of a lateral surface of the conductive wire as taught by Jeon in order protect against formation of a short circuit between the metal layer on left source contact and the metal layer on the gate contact.
Regarding Claim 2:
Lyu discloses wherein the conductive wire has a lower surface facing the substrate and extending beyond the source contact and the conductive via is connected to the lower surface of the conductive wire (the metal layer on the left source contact and left contact to P+ Si doped layer of engineered bulk silicon substrate has lower surface facing the engineered bulk silicon substrate that extends beyond the source contact and the left contact to P+ Si doped layer of engineered bulk silicon substrate is connected to this metal layer, See fig. 1).
Regarding Claim 3:
Lyu discloses wherein the dielectric layer covers a portion of the lower surface of the conductive wire (the portion of the dielectric material layer between the source contact and the left contact to P+ Si doped layer of engineered bulk silicon substrate covers a portion of the metal layer on the left source contact and the left contact to P+ Si doped layer of engineered bulk silicon substrate, See fig. 1).
Regarding Claim 4:
Lyu discloses wherein a portion of the dielectric layer is between the source contact and the conductive via (the portion of the dielectric material layer between the source contact and the left contact to P+ Si doped layer of engineered bulk silicon substrate, See fig. 1).
Regarding Claim 5:
Lyu discloses wherein a portion of the dielectric layer is between the conductive wire and the second nitride semiconductor layer (the portion of the dielectric material layer between the source contact and the left contact to P+ Si doped layer of engineered bulk silicon substrate, See fig. 1).
Regarding Claim 6:
The above stated combination of Lyu and Jeon discloses the above stated semiconductor device. (The examiner notes that figure 1 of Lyu shows a wire leading from the metal layer on the electrically connected together source and drain contacts.)
The above stated combination of Lyu and Jeon does not disclose a second conductive wire on the common contact, wherein the dielectric layer covers at least a portion of the second conductive wire.
Jeon discloses a second conductive wire (an interconnect on an electrode, See fig. 7, ref. nos. 524, 724 and col. 1-19) on the common contact, wherein the dielectric layer covers at least a portion of the second conductive wire (insulating layer covering at least a portion of a lateral portion of the interconnect, See Jeon fig. 7, ref. nos. 700, 724 and col. 8 lines 1-19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device of Lyu and Jeon to include a second conductive wire on the common contact, wherein the dielectric layer covers at least a portion of the second conductive wire as taught by Jeon so that the semiconductor device can be more easily connected to external load such as those shown in figure 1 of Lyu.
Regarding Claim 7:
Lyu discloses wherein a shortest distance between the first gate structure and the common contact is smaller than a shortest distance between the first gate structure and the drain contact (the distance between the right gate and the source contact of the structure formed by the left drain contact, the right source contact, and the metal layer connecting the left drain contact, the right source contact is 2µm and the distance between the right gate and the right drain is 5µm, See Section III, subsection A).
Regarding Claim 8:
Lyu discloses wherein a shortest distance between the second gate structure and the common contact is greater than a shortest distance between the second gate structure and the source contact (the distance between the left gate and the drain contact of the structure formed by the left drain contact, the right source contact, and the metal layer connecting the left drain contact, the right source contact is 5µm and the distance between the left gate and the left source is 2µm, See Section III, subsection A).
Regarding Claim 9:
Lyu discloses wherein a shortest distance between the first gate structure and the common contact is smaller than a shortest distance between the second gate structure and the common contact (the distance between the right gate and the source contact of the structure formed by the left drain contact, the right drain contact, and the metal layer connecting the left drain contact, the right source contact is 2µm and the distance between the left gate and the drain contact of the structure formed by the left drain contact, the right drain contact, and the metal layer connecting the left drain contact, the right source contact is 5µm, See Section III, subsection A).
Regarding Claim 10:
Lyu discloses wherein the source contact is between the second gate structure and the conductive via (the left source contact is between the left gate and the left contact to P+ Si doped layer of engineered bulk silicon substrate, See fig. 1).
Regarding Claim 11:
Lyu discloses wherein the conductive wire is between the source contact and the conductive via (the metal layer is on the dielectric material layer between the left source contact and left contact to P+ Si doped layer of engineered bulk silicon substrate, See fig. 1).
Regarding Claim 12:
Lyu discloses wherein the first gate structure comprises a doped nitride semiconductor element (right rectangular block of Mg doped GaN on the AlGaN layer, See fig. 1 and Section II subsection A) on the second nitride semiconductor layer and a gate contact (metal block on the right rectangular block of Mg doped GaN on the AlGaN layer, See fig. 1 and Section III subsection A.) on the doped nitride semiconductor element.
Regarding Claim 13:
Lyu discloses wherein the second gate structure comprises a doped nitride semiconductor element (left rectangular block of Mg doped GaN on the AlGaN layer, See fig. 1 and Section II subsection A) on the second nitride semiconductor layer and a gate contact on the doped nitride semiconductor element contact (metal block on the left rectangular block of Mg doped GaN on the AlGaN layer, See fig. 1 and Section III subsection B.).
Regarding Claim 14:
Lyu discloses a method of manufacturing a semiconductor device, comprising:
providing a substrate (doping a starting silicon wafer, See Section II subsection A);
forming a first nitride semiconductor layer on the substrate (growing an undoped GaN channel layer, See Section II subsection A);
forming a second nitride semiconductor layer (growing an AlGaN layer, See Section II subsection A) on the first nitride semiconductor layer, wherein the second nitride semiconductor layer has a band gap greater than a band gap of the first nitride semiconductor layer (The AlGaN has a wider band gap than the undoped GaN channel layer to form a 2D electron gas in the undoped GaN channel. The examiner notes the characteristics of the 2D electron gas are shown in table 1.);
forming a drain contact and a source contact on the second nitride semiconductor layer (fabricating the right drain contact and the left source contact, See Section II subsection B and fig. 1);
forming a common contact on the second nitride semiconductor layer and between the drain contact and the source contact (fabricating the left drain contact, the right source contact, and the metal layer electrically connecting the left drain contact and the right source contact, See Section II subsection B and fig. 1), wherein the common contact is a single continuous conductive structure and functions as both the source contact and the drain contact (the structure formed by the left drain contact, the right source contact, and the metal layer is continuous because there are no breaks or gaps in the structure and the structure functions as both a second source contact and a second drain contact because the structure contains both a source contact and a drain contact);
forming a first gate structure on the second nitride semiconductor layer and between the drain contact and the common contact (fabricating the right gate, See Section II subsection B and fig. 1);
forming a second gate structure on the second nitride semiconductor layer and between the common contact and the source contact (fabricating the left gate, See Section II subsection B and fig. 1);
forming a conductive wire on the source contact (fabricating the metal layer on the left source contact and left contact to P+ Si doped layer of the engineered bulk silicon substrate, See Section II subsection B and fig. 1.);
forming a dielectric layer on the second nitride semiconductor layer (fabricating a dielectric material layer on the AlGaN layer, See fig. 1 and Section II, subsection B. The examiner notes that the layer on the AlGaN layer is understood to be a dielectric material layer because the same material fills the trenches shown in figure 1.); and
forming a conductive via connected to the conductive wire, wherein the conductive via extends through a portion of the dielectric layer, the second nitride semiconductor layer, and the first nitride semiconductor layer to the substrate (fabricating the left contact extends through the dielectric material layer, the AlGaN layer, the undoped GaN channel layer to the P+ Si doped layer of the engineered bulk silicon substrate, See Section II subsection B and fig. 1).
Lyu does not disclose the dielectric layer covering a portion of a lateral surface of the conductive wire.
Jeon discloses the dielectric layer covering a portion of a lateral surface of the conductive wire (insulating layer covering a portion of a lateral surface or an interconnect, See fig. 7, ref. nos. 508, 524, 700, and col. 8 lines 1-19).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Lyu to include the dielectric layer covering a portion of a lateral surface of the conductive wire as taught by Jeon in order protect against formation of a short circuit between the metal layer on left source contact and the metal layer on the gate contact.
Regarding Claim 15:
Lyu discloses wherein the conductive wire has a lower surface facing the substrate and extending beyond the source contact and the conductive via is connected to the lower surface of the conductive wire (the metal layer on the left source contact and left contact to P+ Si doped layer of engineered bulk silicon substrate has lower surface facing the engineered bulk silicon substrate that extends beyond the source contact and the left contact to P+ Si doped layer of engineered bulk silicon substrate is connected to this metal layer, See fig. 1).
Regarding Claim 16:
Lyu discloses wherein the dielectric layer covers a portion of the lower surface of the conductive wire (the portion of the dielectric material layer between the source contact and the left contact to P+ Si doped layer of engineered bulk silicon substrate covers a portion of the metal layer on the left source contact and the left contact to P+ Si doped layer of engineered bulk silicon substrate, See fig. 1).
Regarding Claim 17:
Lyu discloses wherein a portion of the dielectric layer is between the source contact and the conductive via (the portion of the dielectric material layer between the source contact and the left contact to P+ Si doped layer of engineered bulk silicon substrate, See fig. 1).
Regarding Claim 18:
The above stated combination of Lyu and Jeon discloses the above stated method of manufacturing a semiconductor device. (The examiner notes that figure 1 of Lyu shows a wire leading from the metal layer on the electrically connected together source and drain contacts.)
The above stated combination of Lyu and Jeon does not disclose forming a second conductive wire on the common contact, wherein the dielectric layer covers at least a portion of the second conductive wire.
Jeon discloses forming a second conductive wire (an interconnect on an electrode, See fig. 7, ref. nos. 524, 724 and col. 1-41) on the common contact, wherein the dielectric layer covers at least a portion of the second conductive wire (insulating layer covering at least a portion of a lateral portion of the interconnect, See Jeon fig. 7, ref. nos. 700, 724 and col. 8 lines 1-41).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of manufacturing a semiconductor device of Lyu and Jeon to include forming a second conductive wire on the common contact, wherein the dielectric layer covers at least a portion of the second conductive wire as taught by Jeon so that the semiconductor device can be more easily connected to external load such as those shown in figure 1 of Lyu.
Regarding Claim 19:
Lyu discloses wherein a shortest distance between the first gate structure and the common contact is smaller than a shortest distance between the first gate structure and the drain contact (the distance between the right gate and the source contact of the structure formed by the left drain contact, the right source contact, and the metal layer connecting the left drain contact, the right source contact is 2µm and the distance between the right gate and the right drain is 5µm, See Section III, subsection A).
Regarding Claim 20:
Lyu discloses wherein a shortest distance between the second gate structure and the common contact is greater than a shortest distance between the second gate structure and the source contact (the distance between the left gate and the drain contact of the structure formed by the left drain contact, the right source contact, and the metal layer connecting the left drain contact, the right source contact is 5µm and the distance between the left gate and the left source is 2µm, See Section III, subsection A).
Response to Arguments
Applicant's arguments filed on July 8, 2026 have been fully considered but they are not persuasive.
The applicant’s arguments that Lyu does not disclose the common contact is a single continuous conductive structure and functions as both the source contact and the drain contact are not persuasive because Lyu discloses this limitation. The examiner notes that Lyu teaches a drain contact of a low side transistor connected to a source contact of a high side transistor by a metal layer. (See Lyu fig. 1). The examiner next notes that the structure formed by the drain contact of the low side transistor, the source contact of the high side transistor, and the metal layer connecting the drain contact of the low side transistor and the source contact of the high side transistor is continuous because there are no breaks or gaps in the structure and the structure functions as both a second source contact and a second drain contact because the structure contains both a source contact and a drain contact. Therefore, applicant’s arguments that Lyu does not disclose the common contact is a single continuous conductive structure and functions as both the source contact and the drain contact are not persuasive because Lyu discloses this limitation.
The applicant’s arguments that Jeon does not disclose a dielectric layer on the second nitride semiconductor layer and covering a portion of a lateral surface of the conductive wire because Jeon discloses a gate structure that is different from the conductive wire recited in claim 1 is not persuasive. The examiner first notes that the combination of Lyu and Jeon is being relied on for teaching a dielectric layer on the second nitride semiconductor layer and covering a portion of a lateral surface of the conductive wire. The examiner next notes that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The examiner now notes that Jeon is not being relied on for teaching a lateral surface of the conductive wire because this structure is already taught by the metal layer on the left source contact and left contact to P+ Si doped layer of the engineered bulk silicon of Lyu. (See Lyu fig. 1). The examiner notes Jeon is being relied on for teaching the dielectric layer covers a portion of a lateral surface of the conductive wire. The examiner further notes that as part of teaching the dielectric layer covers a portion of a lateral surface of the conductive wire Jeon shows, for example, lateral surfaces of the gate electrode covered by an insulating layer in figure 7. Thus, the combination of Lyu and Jeon disclose a dielectric layer on the second nitride semiconductor layer and covering a portion of a lateral surface of the conductive wire. Therefore, applicant’s argument that Jeon does not disclose a dielectric layer on the second nitride semiconductor layer and covering a portion of a lateral surface of the conductive wire is not persuasive because the combination of Lyu and Jeon discloses this limitation.
The applicant’s argument that Jeon does not disclose a common contact on the second nitride semiconductor layer and between the drain contact and the source contact and the common contact is a single continuous conductive structure and functions as both the source contact and the drain contact is not persuasive because the combination of Lyu and Jeon discloses this limitation. The examiner notes that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The examiner next notes this limitation is taught by Lyu, as discussed above, and thus, Jeon is not being relied on to teach this limitation. Therefore, applicant’s argument that Jeon does not disclose a common contact on the second nitride semiconductor layer and between the drain contact and the source contact and the common contact is a single continuous conductive structure and functions as both the source contact and the drain contact is not persuasive because the combination of Lyu and Jeon discloses this limitation.
The applicant’s argument that the measurement point for determining distances from the common contact is not placed at the same location of the common contact is not persuasive because this argument is not supported by the claim language. The examiner notes that claims do not require the distances between the common contact and the first and second gate structures be measured from a same point, such as a center point of the common contact, but rather the claim language includes the distances measured between first and second gate structures and drain and source contacts on the sides of the common contact. Therefore, applicant’s argument that the measurement point for determining distances from the common contact is not placed at the same location of the common contact is not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CALEEN O SULLIVAN/Primary Examiner, Art Unit 2899
/B.S./Examiner, Art Unit 2899
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