Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Requirement for Unity of Invention
Applicant’s election without traverse of claims 1-16 in the reply filed on May 29, 2026 is acknowledged. Claim 17 is withdrawn from further consideration.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 4, 2024 was filed before the mailing of a first Office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The amendment filed on January 4, 2024 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: the light incident surface being flat, See paragraphs 12 and 14 of the preliminary amendment filed on January 4, 2024, and wherein the first semiconductor buried region functions as a window layer, See paragraph 12 of the preliminary amendment filed on January 4, 2024. The examiner notes that the preliminary amendment introduces new matter because new matter is determined as the filing date of the original international application, October 14, 2021, and not as the entry date of the U.S. national stage application, January 4, 2024.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Objections
Claims 1-16 are objected to because of the following informalities: claim 1 recites the limitation “the light incident direction,” on page 5 line 21. There is insufficient antecedent basis for this limitation in the claim. This limitation is understood to be a light incident direction. Appropriate correction is required.
Claims 2-16 are also objected to for containing the same limitation because claims 2-16 depend from claim 1.
Claims 5-6 are objected to because of the following informalities: claim 5 recites the limitation “the upper surface,” on page 6 line 8 and on page 6 line 9. There is insufficient antecedent basis for this limitation in the claim. This limitation is understood to be an upper surface. Appropriate correction is required.
Claim 6 is also objected to for containing the same limitation because claim 6 depends from claim 5.
Claims 10 and 16 are objected to because of the following informalities: claim 10 recites the limitation “the incident light,” on page 7 line 6 and “the surface side,” on page 7 line 6. There is insufficient antecedent basis for these limitations in the claim. These limitations are understood to be an incident light and a surface side. Appropriate correction is required.
Claim 16 is also objected to for containing the same limitations because claim 16 depends from claim 10.
Claims 11-14 are objected to because of the following informalities: claim 11 recites the limitation “the incident light,” on page 7 line 12, “the plan view,” on page 7 line 12, and “the surface side,” on page 7 line 12. There is insufficient antecedent basis for these limitations in the claim. These limitations are understood to be an incident light, a plan view, and a surface side. Appropriate correction is required.
Claim 12-14 are also objected to for containing the same limitations because claim 12-14 depend from claim 11.
Claim 15 is objected to because of the following informalities: claim 15 recites the limitation “the plan view,” on page 8 line 8. There is insufficient antecedent basis for this limitation in the claim. This limitation is understood to be a plan view. Appropriate correction is required.
Claim Rejections - 35 USC § 112
10. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitations “the light incident surface being flat,” on page 5 lines 15-16 and “the first semiconductor buried region functions as a window layer,” on page 5 line 20. The specification does not provide support for these limitations added to claim 1 by the preliminary amendment filed on January 4, 2024. The examiner notes that the preliminary amendment introduces new matter because new matter is determined as the filing date of the original international application, October 14, 2021, and not as the entry date of the U.S. national stage application, January 4, 2024.
Claims 2-16 are also rejected for containing the same limitations because claims 2-16 depend from claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9-11, and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakaji et al. (US2006/0043518).
Regarding Claim 1:
Nakaji discloses a waveguide-type light-receiving element comprising:
a semiconductor substrate (semi-insulative semiconductor substrate, See figs. 2-3, ref. no. 24, paragraphs 35 and 39);
a ridge waveguide (waveguide mesa, See figs. 1-3, ref. no. 16 and paragraph 36) including at least a first-conductivity-type contact layer (n-type InGaAs contact layer, See figs. 2-3, ref. no. 26, paragraphs 40 and 56-58), a first-conductivity-type cladding layer (n-type InP cladding layer, See figs. 2-3, ref. no. 28 and paragraph 40), a light absorption layer (undoped InGaAs light absorption layer, See figs. 2-3 ref. no. 32 and paragraph 40), a second-conductivity-type cladding layer (p-type InP cladding layer, See figs. 2-3, ref. no. 36 and paragraph 40), and a second-conductivity-type contact layer (p-type InGaAs contact layer, See figs. 2-3, ref. no. 40 and paragraph 40), which are laminated above the semiconductor substrate (the n-type InGaAs contact layer, n-type InP cladding layer, undoped InGaAs light absorption layer, p-type InP cladding layer, p-type InGaAs contact layer cover the semi-insulative semiconductor substrate, See figs. 2-3, ref. nos. 24, 26, 28, 32, 36, 40, and paragraph 58), the ridge waveguide having a light incident surface separated from one end of the semiconductor substrate (a front surface formed by an etched stacked central portion of the n-type InP cladding layer, n-type light confining layer, undoped InGaAs light absorption layer, p-type light confining layer, p-type InP cladding layer, p-type InGaAs contact layer is vertically separated from the front end of the semi-insulative semiconductor substrate by the front peripheral portion of the n-type InP cladding layer and the n-type InGaAs contact layer and is horizontally separated from the front end of the semi-insulative semiconductor substrate by the length of the front peripheral portion of the n-type InP cladding layer, See fig. 3, ref. nos. 24, 26, 281, 282, 30, 32, 34, 36, 40, paragraphs 40-41 and 58-60) and a rear surface (a back surface formed by the etched stacked central portion of the n-type InP cladding layer, n-type light confining layer, undoped InGaAs light absorption layer, p-type light confining layer, p-type InP cladding layer, p-type InGaAs contact layer is vertically separated from the back end of the semi-insulative semiconductor substrate by the back peripheral portion of the n-type InP cladding layer and the n-type InGaAs contact layer and is horizontally separated from the back end of the semi-insulative semiconductor substrate by the length of the back peripheral portion of the n-type InP cladding layer and the distance from the end of the back peripheral portion to the back end of the substrate, See fig. 3, ref. nos. 24, 26, 281, 282, 30, 32, 34, 36, 40, paragraphs 40-41 and 58-60) separated from the other end of the semiconductor substrate;
a first semiconductor buried region (region of a blocking layer in contact with the front surface of etched stacked central portion of the n-type InP cladding layer, n-type light confining layer, undoped InGaAs light absorption layer, p-type light confining layer, p-type InP cladding layer, p-type InGaAs contact layer, See fig. 3, ref. no. 281, 30, 32, 34, 36, 38, 40 and paragraph 41) provided in contact with the light incident surface of the ridge waveguide and having a light incident end surface (light receiving side end face, See fig. 3, ref. no. 38a and paragraphs 44-46) that is one surface on a light incident side and is separated from the one end of the semiconductor substrate (the light receiving side end face is vertically separated from the front end of the semi-insulative semiconductor substrate by the front peripheral portion of the n-type InP cladding layer and the n-type InGaAs contact layer, See fig. 3, ref. nos. 26, 30, 38a, 282), the light incident surface being flat (the light receiving side end face is shown as a flat surface, See fig. 1 and fig. 3, ref. no. 38a); and
a second semiconductor buried region (region of the blocking layer in contact with the back surface of the etched stacked central portion of the n-type InP cladding layer, n-type light confining layer, undoped InGaAs light absorption layer, p-type light confining layer, p-type InP cladding layer, p-type InGaAs contact layer, See fig. 3, ref. no. 281, 30, 32, 34, 36, 38, 40 and paragraph 41) provided in contact with the rear surface of the ridge waveguide and having a rear end surface (rear sidewall surface, See fig. 3, ref. no. 38b and paragraph 48) that is one surface facing the rear surface and is separated from the other end of the semiconductor substrate (the rear sidewall surface is vertically separated from the back end of the semi-insulative semiconductor substrate by the back peripheral portion of the n-type InP cladding layer and the n-type InGaAs contact layer and is horizontally separated from the back end of the semi-insulative semiconductor substrate by the length of the right portion of the peripheral portion of the n-type InP cladding layer and the distance from the end of the right portion of the peripheral portion to the back end of the substrate, See fig. 3, ref. nos. 24, 26, 281, 282, 30, 38b, 40 and paragraphs 40-41), wherein
the first semiconductor buried region functions as a window layer (light travels through region of blocking layer in contact with the front surface of etched stacked central portion of the n-type InP cladding layer, n-type light confining layer, undoped InGaAs light absorption layer, p-type light confining layer, p-type InP cladding layer, p-type InGaAs contact layer, See fig. 3, ref. nos. 14, 281, 30, 32, 34, 36, 38 and paragraphs 44-45) where a layer thickness of the first semiconductor buried region in the light incident direction is a window length (the thickness of the region of blocking layer in contact with the front surface of etch stacked central portion of the n-type InP cladding layer, n-type light confining layer, undoped InGaAs light absorption layer, p-type light confining layer, p-type InP cladding layer, p-type InGaAs contact layer measured from front to back is a window length, See fig. 3, ref. nos. 281, 30, 32, 34, 36, 38, 40).
Regarding Claim 2:
Nakaji discloses wherein the light incident surface and the rear surface of the ridge waveguide are each formed of an etched surface (the front surface and the back surface are formed by etching the stacked the n-type InP cladding layer, n-type light confining layer, undoped InGaAs light absorption layer, p-type light confining layer, p-type InP cladding layer, and p-type InGaAs contact layer, See fig. 4, ref. nos. 281, 282, 30, 32, 34, 36, 40, and paragraphs 58-60).
Regarding Claim 3:
Nakaji discloses wherein the light incident end surface of the first semiconductor buried region and the rear end surface of the second semiconductor buried region are each formed of an etched surface (the light receiving side end face and the rear sidewall surface of the blocking layer are formed by etching, See figs. 6-7, ref no. 38 and paragraphs 63-66).
Regarding Claim 9:
Nakaji discloses the light incident end surface of the first semiconductor buried region is an inclined plane with respect to the surface of the semiconductor substrate (the light receiving side end face is inclined at 90 degrees with respect to the top surface of the semi-insulative semiconductor substrate, See fig. 1, fig. 3, ref. nos. 24 and 38a).
Regarding Claim 10:
Nakaji discloses the light incident end surface of the first semiconductor buried region is provided in a direction perpendicular to the incident light in a plan view from the surface side of the semiconductor substrate (the light receiving side end face is perpendicular to a direction of the signal light in a plan view from the top surface of the semi-insulative semiconductor substrate, See fig. 1, ref. no. 14, fig. 3, ref. nos. 14, 24, 38a).
Regarding Claim 11:
Nakaji discloses the light incident end surface of the first semiconductor buried region is provided in a direction inclined with respect to the incident light in the plan view from the surface side of the semiconductor substrate (the light receiving side end face is inclined at 90 degrees with respect to a direction of the signal light in a plan view from the top surface of the semi-insulative semiconductor substrate, See fig. 1, ref. no. 14, fig. 3, ref. nos. 14, 24, 38a).
Regarding Claim 14:
Nakaji discloses wherein the rear end surface of the second semiconductor buried region is provided in a direction inclined at a different angle from the light incident end surface of the first semiconductor buried region in the plan view from the surface side of the semiconductor substrate (the rear sidewall surface is inclined at an angle greater than 90 degrees and the light receiving side end face is inclined at 90 degrees in a plan view from the top surface of the semi-insulative semiconductor substrate , See fig. 1, ref. no. 14, fig. 3, ref. nos. 14, 24, 38a, 38b).
Regarding Claim 15:
Nakaji discloses wherein the ridge waveguide is inclined in a direction facing light incident on the ridge waveguide in the plan view from the surface side of the semiconductor substrate (the front of the waveguide mesa is inclined at 90 degrees with respect to a direction of the signal light in a plan view from the top surface of the semi-insulative semiconductor substrate, See figs. 1, 3, ref. nos. 14 and 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 8-11, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi (US 2002/0050622) in view of Kajima et al. (JPH 11274552 A). The examiner notes that the citations to paragraphs of Kajima refer to paragraphs in the attached English language translation of Kajima.
Regarding Claim 1:
Takeuchi discloses a waveguide-type light-receiving element comprising:
a semiconductor substrate (semi-insulating semiconductor substrate, See fig. 3, ref. no. 1 and paragraph 99);
a ridge waveguide (waveguide mesa structure, See fig. 3, ref. no. 100, paragraphs 99 and 116-117) including at least a first-conductivity-type contact layer (n-type InAlGaAs optical guide layer, See fig. 3, ref. no. 3 and paragraph 117), a first-conductivity-type cladding layer (n-type InP cladding layer, See fig. 3, ref no. 2 and paragraph 117), a light absorption layer (undoped InGaAs optical absorption layer, See fig. 3, ref. no. 4 and paragraph 117), a second-conductivity-type cladding layer (p-type InP cladding layer, See fig. 3, ref. no. 6 and paragraph 117), and a second-conductivity-type contact layer (p-type InGaAs contact layer, See fig. 3, ref. no. 7 and paragraph 117), which are laminated above the semiconductor substrate (the n-type InAlGaAs optical guide layer, n-type InP cladding layer, undoped InGaAs optical absorption layer, p-type InP cladding layer, p-type InGaAs contact layer cover the semi-insulating semiconductor substrate, See figs. 3, ref. nos. 1, 2, 3, 4, 6, 7, and paragraph 117), the ridge waveguide having a light incident surface (the front face formed by stacked n-type InP cladding layer, n-type InAlGaAs optical guide layer, undoped InGaAs optical absorption layer, p-type InAlGaAs optical guide layer, p-type InP cladding layer, p-type InGaAs contact layer is horizontally separated from the front end of the semi-insulating semiconductor substrate by the length of a portion of the heat radiation semiconductor layer in front of the stacked layers, See fig. 3, ref. nos. 1, 2, 3, 4, 5, 6, 7, 9 and paragraph 102) separated from one end of the semiconductor substrate and a rear surface separated from the other end of the semiconductor substrate the ridge waveguide having a light incident surface (the back face formed by stacked n-type InP cladding layer, n-type InAlGaAs optical guide layer, undoped InGaAs optical absorption layer, p-type InAlGaAs optical guide layer, p-type InP cladding layer, p-type InGaAs contact layer is horizontally separated from the back end of the semi-insulating semiconductor substrate by the lengths of portions of the heat radiation semiconductor layer behind the stacked layers and the length of the first groove See fig. 2, fig. 3, ref. nos. 1, 2, 3, 4, 5, 6, 7, 9, 220 and paragraphs 104-107);
a first semiconductor buried region (portion of heat radiation semiconductor layer in front of the by stacked n-type InP cladding layer, n-type InAlGaAs optical guide layer, undoped InGaAs optical absorption layer, p-type InAlGaAs optical guide layer, p-type InP cladding layer, p-type InGaAs contact layer is in contact with the front face formed by the stacked layers, See fig. 3, ref. nos. 2, 3, 4, 5, 6, 7, 9 and paragraph 102) provided in contact with the light incident surface of the ridge waveguide and having a light incident end surface (front face of the portion of the heat radiation semiconductor layer in front of the stacked layers, See fig. 3, ref. nos. 2, 3, 4, 5, 6, 7, and 9) that is one surface on a light incident side and is flat (the front face of the portion of the heat radiation semiconductor layer in front of the stacked layers shown as a flat surface, See fig. 2 and fig. 3, ref. no. 9); and
a second semiconductor buried region (portion of heat radiation semiconductor layer in between the stacked n-type InP cladding layer, n-type InAlGaAs optical guide layer, undoped InGaAs optical absorption layer, p-type InAlGaAs optical guide layer, p-type InP cladding layer, p-type InGaAs contact layer and the first groove is in contact with the back face formed by the stacked layers, See fig. 3, ref. nos. 2, 3, 4, 5, 6, 7, 9, 220 and paragraphs 104-107) provided in contact with the rear surface of the ridge waveguide and having a rear end surface (back face of the portion of the heat radiation semiconductor layer between the stacked n-type InP cladding layer, n-type InAlGaAs optical guide layer, undoped InGaAs optical absorption layer, p-type InAlGaAs optical guide layer, p-type InP cladding layer, p-type InGaAs contact layer and the first groove faces the back face formed by the stacked layers, See fig. 3, ref. nos. 2, 3, 4, 5, 6, 7, 9, 220) that is one surface facing the rear surface and is separated from the other end of the semiconductor substrate (the back face of the portion of the heat radiation semiconductor layer between the stacked n-type InP cladding layer, n-type InAlGaAs optical guide layer, undoped InGaAs optical absorption layer, p-type InAlGaAs optical guide layer, p-type InP cladding layer, p-type InGaAs contact layer and the first groove is separated from the back end of the semi-insulating semiconductor substrate by the length of the first groove and the length of the heat radiation semiconductor layer following the first groove, See figs. 2, fig. 3, ref. nos. 1, 9 and 220), wherein
the first semiconductor buried region functions as a window layer (light travels through portion of the heat radiation semiconductor layer in front of the stacked n-type InP cladding layer, n-type InAlGaAs optical guide layer, undoped InGaAs optical absorption layer, p-type InAlGaAs optical guide layer, p-type InP cladding layer, p-type InGaAs contact layer, See fig. 3, ref. nos. 2, 3, 4, 5, 6 ,7, 9, and paragraph 107) where a layer thickness of the first semiconductor buried region in the light incident direction is a window length (the thickness of the portion of the heat radiation semiconductor layer in front of the stacked n-type InP cladding layer, n-type InAlGaAs optical guide layer, undoped InGaAs optical absorption layer, p-type InAlGaAs optical guide layer, p-type InP cladding layer, p-type InGaAs contact layer measured from front to back is a window length, See fig. 3, ref. nos. 2, 3, 4, 5, 6 ,7, and 9).
Takeuchi does not disclose the light incident end surface is separated from the one end of the semiconductor substrate.
Kajima discloses forming a light-emitting diode set back from the ends of a substrate so that the light-emitting diode can be formed with more precise dimensions (See fig. 1, ref. nos. 10, 12, paragraphs 3-5 and 28-30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the waveguide-type light-receiving element of Takeuchi to form the structure of the waveguide-type light receiving element that formed on the semi-insulating semiconductor substrate set back from the ends of the semi-insulating semiconductor substrate as taught by Kajima so that the dimensions of the structures formed on the semi-insulating semiconductor substrate can be precisely formed by precise fabrication techniques while the semi-insulating semiconductor substrate can be separated using a less precise fabrication technique. (See Takeuchi paragraphs 3-7 and 49.)
Regarding Claim 4:
Takeuchi discloses wherein the light incident end surface of the first semiconductor buried region (front face of heat radiation semiconductor layer in front of stacked layers, See fig. 3, ref. no. 2, 3, 4, 5, 6, 7, 9, and paragraph 102 and 116-117) is covered with an anti-reflection film (anti-reflective film, See fig. 3, ref. no. 17 and paragraph 107).
Regarding Claim 5:
Takeuchi discloses wherein at least the light incident end surface and the upper surface of the first semiconductor buried region, and the rear end surface and the upper surface of the second semiconductor buried region are covered with a passivation film (a silicon nitride film covers the front face of the portion of the heat radiation semiconductor layer in front of the stacked layers, the portion of the heat radiation semiconductor layer in front of the stacked layers, the back face of the portion of the heat radiation semiconductor layer between stacked layers and the first groove, and the upper surface of the portion of the heat radiation semiconductor layer between the stacked layers and the first groove, See fig. 3, ref. nos. 2, 3, 4, 5, 6, 7, 9, 11, 220 and paragraph 106. The examiner notes that the front end of the silicon nitride film is shown flush with the front face of the portion of the heat radiation semiconductor layer in front of the stacked layer, thus, the silicon nitride film cover the front face because no portion of the front face extends beyond the front end of the silicon nitride film.)
Regarding Claim 6:
Takeuchi discloses a surface electrode (second polarity electrode structure, See fig. 3, ref. nos. 12, 14a, 15a, 16 and paragraph 120) is provided at least on a surface of the second-conductivity-type contact layer.
Regarding Claim 8:
Takeuchi discloses at least a bottom portion of the first semiconductor buried region is in contact with the semiconductor substrate (a bottom portion of the heat radiation semiconductor layer in front of the stack layers is in contact with the semi-insulating semiconductor substrate, See fig. 3, ref. nos. 1, 2, 3, 4, 5, 6, 7, and 9).
Regarding Claim 9:
Takeuchi discloses the light incident end surface of the first semiconductor buried region is an inclined plane with respect to the surface of the semiconductor substrate (front face of heat radiation semiconductor layer in front of stacked layers is inclined at 90 degrees with respect to the top surface of the semi-insulating semiconductor substrate, See fig. 3, ref. no. 1, 2, 3, 4, 5, 6, 7, 9).
Regarding Claim 10:
Takeuchi discloses the light incident end surface of the first semiconductor buried region is provided in a direction perpendicular to the incident light in a plan view from the surface side of the semiconductor substrate (front face of heat radiation semiconductor layer in front of stacked layers is perpendicular to a direction of the incident light in a plan view from the top surface of the semi-insulating semiconductor substrate, See fig. 2, fig. 3, ref. no. 1, 2, 3, 4, 5, 6, 7, 9).
Regarding Claim 11:
Takeuchi discloses the light incident end surface of the first semiconductor buried region is provided in a direction inclined with respect to the incident light in the plan view from the surface side of the semiconductor substrate (front face of heat radiation semiconductor layer in front of stacked layers is inclined at 90 degrees with respect to a direction of the incident light in a plan view from the top surface of the semi-insulating semiconductor substrate, See fig. 2, fig. 3, ref. no. 1, 2, 3, 4, 5, 6, 7, 9).
Regarding Claim 13:
Takeuchi discloses wherein the rear end surface of the second semiconductor buried region is provided in a direction parallel to the light incident end surface of the first semiconductor buried region in the plan view from the surface side of the semiconductor substrate (front face of heat radiation semiconductor layer in front of stacked layers and the back face of the portion of the heat radiation semiconductor layer between the stacked layer and the first groove are inclined at 90 degrees with respect to a direction of the incident light in a plan view from the top surface of the semi-insulating semiconductor substrate, See fig. 2, fig. 3, ref. no. 1, 2, 3, 4, 5, 6, 7, 9).
Regarding Claim 15:
Takeuchi discloses wherein the ridge waveguide is inclined in a direction facing light incident on the ridge waveguide in the plan view from the surface side of the semiconductor substrate (the front of the waveguide mesa structure is inclined at 90 degrees with respect to a direction of the incident light in a plan view from the top surface of the semi-insulating semiconductor substrate, See figs. 2, fig. 3, ref. no. 100 and paragraph 98).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi (US 2002/0050622) and Kajima et al. (JPH 11274552 A) in view of Sasaki (US 2015/0357525).
Regarding Claim 7:
The above stated combination of Takeuchi and Kajima discloses the above stated waveguide-type light-receiving element.
The above stated combination of Takeuchi and Kajima does not disclose a back surface metal is provided on a back surface side of the semiconductor substrate.
Sasaki discloses a protective layer made of metal on a back surface side of a light emitting diode chip (See fig. 12, ref. nos. 100, 109 and paragraphs 4 and 15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the waveguide-type light receiving element of Takeuchi and Kajima to include a protective layer made of metal on the back surface side of the semi-insulative semiconductor substrate as taught by Sasaki in order to protect the waveguide semiconductor photodetector from being damaged.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over by Nakaji et al. (US2006/0043518) in view of Sasaki (US 2015/0357525).
Regarding Claim 7:
Nakaji discloses the above stated waveguide-type light-receiving element.
Nakaji does not disclose a back surface metal is provided on a back surface side of the semiconductor substrate.
Sasaki discloses a protective layer made of metal on a back surface side of a light emitting diode chip (See fig. 12, ref. nos. 100, 109 and paragraphs 4 and 15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the waveguide-type light receiving element of Nakaji to include a protective layer made of metal on the back surface side of the semi-insulative semiconductor substrate as taught by Sasaki in order to protect the waveguide semiconductor photodetector from being damaged.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Takeuchi (US 2002/0050622) and Kajima et al. (JPH 11274552 A) in view of Komaba et al. (JP 2002033504 A). The examiner notes that the citations to paragraphs of Komaba refer to paragraphs of the attached English language translation.
Regarding Claim 16:
The combination of Takeuchi and Kajima discloses a waveguide-type light receiving element according to claim 10. See the above stated rejection of claim 10 under 35 U.S.C. 103 as being unpatentable over Takeuchi (US 2002/0050622) and Kajima et al. (JPH 11274552 A).
The combination of Takeuchi and Kajima does not disclose a plurality of the waveguide-type light receiving elements according to claim 10 integrated in parallel such that the ridge waveguides of the waveguide-type light receiving elements are located parallel to each other..
Komaba discloses light-receiving element array with a plurality of waveguide-type photodetectors positioned in parallel on the same substrate (See fig. 3, ref. nos. 30, 32, and paragraphs 14-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the waveguide-type light receiving element of Takeuchi and Kajima to include a plurality of the waveguide-type light receiving elements according to claim 10 positioned in parallel on the same substrate as taught by Komaba in order to demultiplex optical signals. (See Komaba paragraph 2.)
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over by Nakaji et al. (US2006/0043518) in view of Komaba et al. (JP 2002033504 A).
Regarding Claim 16:
Nakaji discloses a waveguide-type light receiving element according to claim 10. See the above stated rejection of claim 10 under 35 U.S.C. 102(a)(1) as being anticipated by Nakaji et al. (US2006/0043518).
Nakaji does not disclose a plurality of the waveguide-type light receiving elements according to claim 10 integrated in parallel such that the ridge waveguides of the waveguide-type light receiving elements are located parallel to each other..
Komaba discloses light-receiving element array with a plurality of waveguide-type photodetectors positioned in parallel on the same substrate (See fig. 3, ref. nos. 30, 32, and paragraphs 14-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the waveguide-type light receiving element of Nakaji to include a plurality of the waveguide-type light receiving elements according to claim 10 positioned in parallel on the same substrate as taught by Komaba in order to demultiplex optical signals. (See Komaba paragraph 2.)
Conclusion
****** Note - no prior art has been applied to dependent claim 12 as the subject matter of claim 12 including all of the limitations of the base claim and any intervening claims appears to overcome the prior art. However, as described above, the amendments to independent claim 1, which claim 12 depends from, in the preliminary amendment filed on January 4, 2024 raise rejections 35 U.S.C. 112(a) rejections. Once these rejections and the above stated objections to claim 12 are overcome, it is possible that claim 12 would be in condition for allowance.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRETT SQUIRES whose telephone number is (571)272-8214. The examiner can normally be reached Mon-Fri 8:00am-5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.S./Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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