Prosecution Insights
Last updated: July 17, 2026
Application No. 18/576,761

SILICON CARBIDE SEMICONDUCTOR DEVICE AND ELECTRIC POWER CONVERTER

Non-Final OA §102§103
Filed
Jan 05, 2024
Priority
Jul 15, 2021 — nonprovisional of PCTJP2021026592
Examiner
MENZ, DOUGLAS M
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
686 granted / 776 resolved
+20.4% vs TC avg
Minimal +5% lift
Without
With
+4.6%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
32 currently pending
Career history
807
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
52.1%
+12.1% vs TC avg
§102
36.2%
-3.8% vs TC avg
§112
0.6%
-39.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 776 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 18, 21, 26, 28, 29, 32, 34 and 35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Meiser et al. (US 2020/0176568). Regarding claim 1, Meiser discloses a silicon carbide semiconductor device comprising: an n-type silicon carbide substrate having a first main surface and a second main surface that are opposed to each other (127, figs. 1-7 and paragraph 0061); an SJ region formed of silicon carbide and provided on the first main surface of the silicon carbide substrate (120, figs. 1-7 and paragraph 0060); and an MOSFET region provided on an upper surface of the SJ region, wherein the SJ region includes a plurality of n-type first pillar regions (1161, figs. 1-7 and paragraph 0060) and a plurality of p-type second pillar regions (114, figs. 1-8 and paragraph 0054) that extend in a first direction parallel to the first main surface and that are alternately aligned in a second direction parallel to the first main surface and perpendicular to the first direction, and the MOSFET region includes: a plurality of BPW regions formed of p-type silicon carbide (112, figs. 1-7 and paragraph 0054), extending in the second direction, connected to the plurality of second pillar regions, and aligned in the first direction at a second repetition interval that is shorter than a first repetition interval that is a repetition interval of the plurality of second pillar regions (figs. 7-8 and paragraph 0071); and a plurality of gate electrodes provided via a gate insulating film in a plurality of trenches (110, figs. 1-7 and paragraph 0055), respectively, that are provided in the second direction above the plurality of BPW regions (112, figs. 1-7), respectively. Regarding claim 18, Meiser further discloses wherein the plurality of BPW regions (112, figs. 1-7) are connected to the plurality of second pillar regions (114, figs. 1-7). Regarding claim 21, Meiser further discloses wherein each of the plurality of second pillar regions (114, figs. 1-7) and each of the plurality of BPW regions (112, figs. 1-7) are directly connected to each other. Regarding claim 26, Meiser further discloses wherein each of the plurality of second pillar regions (114, figs. 1-7) and each of the plurality of BPW region (112, figs. 1-7) are directly connected to each other in 80% or more in number of the intersections of the plurality of second pillar regions and the plurality of BPW regions. Regarding claim 28, Meiser discloses a silicon carbide semiconductor device comprising: an n-type silicon carbide substrate having a first main surface and a second main surface that are opposed to each other (127, figs. 1-7 and paragraph 0061); an SJ region formed of silicon carbide and provided on the first main surface of the silicon carbide substrate (120, figs. 1-7 and paragraph 0060); and an MOSFET region provided on an upper surface of the SJ region, wherein the SJ region includes a plurality of n-type first pillar regions (1161, figs. 1-7 and paragraph 0060) and a plurality of p-type second pillar regions (114, figs. 1-8 and paragraph 0054) that extend in a first direction parallel to the first main surface and that are alternately aligned in a second direction parallel to the first main surface and perpendicular to the first direction, and the MOSFET region includes: a plurality of body regions formed of p-type silicon carbide (112, figs. 1-7 and paragraph 0054), extending in the second direction, and aligned in the first direction at a second repetition interval that is shorter than a first repetition interval that is a repetition interval of the plurality of second pillar regions (figs. 7-8 and paragraph 0071). Regarding claim 29, Meiser further discloses wherein the plurality of body regions (112, figs. 1-7) are connected to each of the plurality of second pillar regions (114, figs. 1-7). Claim 34. (New) The silicon carbide semiconductor device according to claim 1, wherein each of the plurality of second pillar regions and each of the plurality of body regions are directly connected to each other in 80% or more in number of intersections of the plurality of second pillar regions and the plurality of body regions. Regarding claim 32, Meiser further discloses wherein each of the plurality of second pillar regions (114, figs. 1-7) and each of the plurality of body regions (112, figs. 1-7) are directly connected to each other. Regarding claim 34, (note: claim 34 is dependent on claim 1, Examiner believes this is in error because of the 112 issues, Examiner assumes dependent on claim 28, please correct dependency or 112) Meiser further discloses wherein each of the plurality of second pillar regions (114, figs. 1-7) and each of the plurality of body regions are directly connected via each of the plurality of body contact regions to each other in 80% or more in number of intersections of the plurality of second pillar regions and the plurality of body regions. Regarding claim 35, (note: claim 35 is dependent on claim 1, Examiner believes this is in error because of the 112 issues, Examiner assumes dependent on claim 28, please correct dependency or 112) Meiser further discloses wherein each of the plurality of second pillar regions (114, figs. 1-7) and each of the plurality of body regions are connected via each of the plurality of body contact regions to each other in 80% or more in number of intersections of the plurality of second pillar regions and the plurality of body regions. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Meiser et al. (US 2020/0176568). Regarding claim 36, Meiser discloses the silicon carbide semiconductor device according to claim 1, as mentioned above. Meiser does not explicitly disclose such a device implemented into a main conversion circuit with a driving and control circuit of claim 36. However, such implantation would be deemed obvious to one of ordinary skill in the art at the time of filing since such circuitry was common in the art. Allowable Subject Matter Claims 19-20, 22-25, 27, 30-31 and 33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 19, there is no teaching or suggestion in the art of record disclosing the silicon carbide semiconductor device according to claim 1, wherein the MOSFET region includes: a plurality of JFET regions formed of n-type silicon carbide and extending in the second direction between each adjacent two of the plurality of BPW regions and between each adjacent two of the plurality of trenches; a plurality of body regions formed of p-type silicon carbide and provided on and in contact with the plurality of JFET regions, respectively; and at least one connection region formed of p-type silicon carbide, provided in contact with at least one of the plurality of JFET regions, and connecting at least one of the plurality of BPW regions and at least one of the plurality of body regions. Regarding claim 20, (note: claim 20 is dependent on claim 1, Examiner believes this is in error because of the 112 issues, Examiner assumes dependent on claim 19 and therefore allowable, please correct dependency or 112). Claims 22-25 and 27 depend on claim 19. Regarding claim 30, there is no teaching or suggestion in the art of record disclosing the silicon carbide semiconductor device according to claim 28, wherein the MOSFET region includes a plurality of JFET regions formed of n-type silicon carbide and provided between the plurality of body regions. Regarding claim 31, (note: claim 31 is dependent on claim 28, Examiner believes this is in error because of the 112 issues, Examiner assumes dependent on claim 30 and therefore allowable, please correct dependency or 112). Claim 33 depends on claim 31. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publications 20150171169 and 20070013412 both disclose relevant silicon carbide devices with super junction structures. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 6/13/26
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Prosecution Timeline

Jan 05, 2024
Application Filed
Jun 17, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
93%
With Interview (+4.6%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 776 resolved cases by this examiner. Grant probability derived from career allowance rate.

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