Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 5th, 2024, was filed prior to the mailing date of the first office action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1 and 3-10 are rejected under 35 U.S.C. 103 as being unpatentable over Nakata (2020/0058742 A1; hereinafter Nakata) in view of Ota (2022/0102502 A1; hereinafter Ota).
Regarding Claim 1, Nakata (annotated figs. 1-2) teaches a semiconductor device ([0052], 91) comprising:
a semiconductor substrate ([0052], 10) that includes a semiconductor element ([0053], 16, 17) being at least one of a transistor and a diode ([0052], [0135], defined as an SBD, or Schottky barrier diode, may instead be a transistor);
a trench gate that includes an electrode (17) to control a state of the semiconductor element (16, 17) and is provided in an upper surface of the semiconductor substrate (top surface of 10, see fig. 2);
a first amorphous layer ([0060], 20 formed on left and right sides of 91, referred to as first amorphous layer, see annotated fig. 1) that is disposed in each of two opposing first side surfaces (left and right sides of 91, see annotated fig. 1) from among four side surfaces of the semiconductor substrate (10); and
a second amorphous layer ([0060], 20 formed on top and bottom sides of 91, referred to as second amorphous layer, see annotated fig. 1) that is disposed in each of two opposing second side surfaces (top and bottom sides of 91, see annotated fig. 1) other than the first side surfaces (left and right sides of 91) from among the four side surfaces of the semiconductor substrate (10), wherein in plan view,
a first angle between each of the first side surfaces and a direction of extension of the trench gate is smaller than a second angle between each of the second side surfaces and the direction of extension of the trench gate, or each of the first side surfaces is parallel to the direction of extension of the trench gate, and
a thickness of the first amorphous layer ([0061], thickness of 22 in first amorphous layer) in a direction (left and right, see annotated fig. 1) from each of the first side surfaces toward an inside of the semiconductor substrate (10) is different ([0061], thickness of 22 is greater than a thickness of 21, see fig. 2) from a thickness of the second amorphous layer ([0061], thickness of 21 in second amorphous layer) in a direction (up and down, see annotated fig. 1) from each of the second side surfaces toward the inside of the semiconductor substrate (10).
Nakata doesn’t teach a trench gate includes an electrode to control a state of the semiconductor element and each of the first side surfaces is parallel to the direction of extension of the trench gate.
However, Ota (fig. 14) teaches a trench gate ([0258], 111) includes an electrode ([0261], 114) to control a state of the semiconductor element ([0252], transistor 102) and each of the first side surfaces (left and right side surfaces of 101) is parallel to the direction of extension ([0258], x direction) of the trench gate (111). Ota also teaches that MISFET having a trench gate may replace a schottky barrier diode while obtaining the predictable result of a functional semiconductor device ([0252]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the trench gate MISFET of Ota for the SBD of Nakata, since simple substitution of semiconductor elements for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
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Annotated Figure 1
Regarding Claim 3, Nakata (annotated figs. 1-2) teaches the semiconductor device according to claim 1, wherein the thickness of the second amorphous layer (thickness of 21 in second amorphous layer) is less than or equal to 1.1 times (the thickness of 22 is larger than the thickness of 21, therefore the thickness of the second amorphous layer is between 0 and 1 times the thickness of the first amorphous layer) the thickness of the first amorphous layer (thickness of 22 in first amorphous layer).
Regarding Claim 4, Nakata (annotated figs. 1-2) teaches the semiconductor device according to claim 1, wherein the thickness of the first amorphous layer (thickness of 22 in first amorphous layer) is 0.05 μm or more ([0061], may be 0.1 μm or greater).
Regarding Claim 5, Nakata (annotated figs. 1-2) teaches the semiconductor device according to claim 1 further comprising a single-crystal layer (portion of 12 formed above 22 in second amorphous layer, see fig. 2) that is disposed above the second amorphous layer (second amorphous layer) in each of the second side surfaces.
Regarding Claim 6, Nakata (annotated figs. 1-2) teaches the semiconductor device according to claim 1, wherein the first amorphous layer (first amorphous layer) and the second amorphous layer (second amorphous layer) are formed of an amorphous material including the same element ([0060], 20 is formed of the same material as the substrate, such as SiC) as an element forming a crystal of the semiconductor substrate (10).
Regarding Claim 7, Nakata (annotated figs. 1-2) teaches the semiconductor device according to claim 1, wherein
the semiconductor substrate includes (10) a drift layer ([0054], 11),
the first amorphous layer (first amorphous layer) includes an upper first amorphous layer (21 in first amorphous layer) that is disposed in a side surface of the drift layer (11) and a lower first amorphous layer (22 in first amorphous layer) that is disposed closer (22 is below 21) to a lower surface of the semiconductor substrate (10) than the upper first amorphous layer (21 in first amorphous layer) is,
the second amorphous layer (second amorphous layer) includes an upper second amorphous layer (21 in second amorphous layer) that is disposed in a side surface of the drift layer (11) and a lower second amorphous layer (22 in second amorphous layer) that is disposed closer (22 is below 21) to the lower surface of the semiconductor substrate (10) than the upper second amorphous layer (21 in second amorphous layer) is, and
a thickness of the upper first amorphous layer (thickness of 21 in first amorphous layer) in the direction (left and right, see annotated fig. 1) from each of the first side surfaces toward the inside of the semiconductor substrate (10) is smaller ([0061], thickness of 22 is greater than a thickness of 21, see fig. 2) than a thickness of the lower first amorphous layer (thickness of 22 in first amorphous layer) in the direction (left and right) from each of the first side surfaces toward the inside of the semiconductor substrate (10).
Regarding Claim 8, Nakata (annotated figs. 1-2) teaches the semiconductor device according to claim 1, wherein
the semiconductor substrate includes (10) a drift layer ([0054], 11),
the first amorphous layer (first amorphous layer) includes an upper first amorphous layer (21 in first amorphous layer) that is disposed in a side surface of the drift layer (11) and a lower first amorphous layer (22 in first amorphous layer) that is disposed closer (22 is below 21) to a lower surface of the semiconductor substrate (10) than the upper first amorphous layer (21 in first amorphous layer) is,
the second amorphous layer (second amorphous layer) includes an upper second amorphous layer (21 in second amorphous layer) that is disposed in a side surface of the drift layer (11) and a lower second amorphous layer (22 in second amorphous layer) that is disposed closer (22 is below 21) to the lower surface of the semiconductor substrate (10) than the upper second amorphous layer (21 in second amorphous layer) is, and
a thickness of the upper second amorphous layer (thickness of 21 in second amorphous layer) in the direction (up and down, see annotated fig. 1) from each of the second side surfaces toward the inside of the semiconductor substrate (10) is smaller ([0061], thickness of 22 is greater than a thickness of 21, see fig. 2) than a thickness of the lower second amorphous layer (thickness of 22 in second amorphous layer) in the direction (left and right) from each of the second side surfaces toward the inside of the semiconductor substrate (10).
Regarding Claim 9, Nakata (fig. 34) teaches a power converter ([0160], 200) comprising:
a main conversion circuit ([0162], 201) that converts input power for output ([0162]), the main conversion circuit (201) including the semiconductor device ([0164], 202) according to claim 1;
a drive circuit ([0165], drive circuit, not shown) that outputs a drive signal to drive the semiconductor device (202) to the electrode ([0164]-[0165], drive circuit drives the electrodes of the switching elements, which may be 202) of the semiconductor element (diode of claim 1) of the semiconductor device (202); and
a control circuit ([0162], 203) that outputs a control signal to control ([0166]) the drive circuit to the drive circuit (drive circuit).
Regarding Claim 10, Nakata (annotated figs. 1-2) teaches the semiconductor device according to claim 7, wherein a thickness of the upper second amorphous layer (thickness of 21 in second amorphous layer) in the direction (up and down, see annotated fig. 1) from each of the second side surfaces toward the inside of the semiconductor substrate (10) is smaller than a thickness of the lower second amorphous layer (thickness of 22 in second amorphous layer) in the direction (up and down) from each of the second side surfaces toward the inside of the semiconductor substrate (10).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter. None of the references cited, either singly or in combination, teach or render obvious the limitations in Claim 2 wherein “the first amorphous layer and the second amorphous layer are arranged outside the interlayer dielectric film in plan view and are separated from an outer edge of the interlayer dielectric film by 3 μm or more”.
Conclusion
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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