Prosecution Insights
Last updated: April 19, 2026
Application No. 18/577,884

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Jan 09, 2024
Examiner
FOX, BRANDON C
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
96%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
686 granted / 800 resolved
+17.8% vs TC avg
Moderate +10% lift
Without
With
+10.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
24 currently pending
Career history
824
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
56.9%
+16.9% vs TC avg
§102
33.9%
-6.1% vs TC avg
§112
5.9%
-34.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 800 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is a Non-Final office action based on application 18/577,884 filed January 9, 2024. Claims 1-9 are currently pending and have been considered below. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3 & 7-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Maeda (WO 2021/075016). Regarding claim 1, Maeda discloses a semiconductor device comprising: an insulating substrate (Fig. 6, 4a) having a circuit pattern (4b/4c); a plurality of semiconductor elements (10) bonded onto the circuit pattern via first bonded portions (9); and a lead electrode (8) to which each of the plurality of semiconductor elements is bonded via a second bonded portion (11), wherein the lead electrode is composed of a plurality of lead electrode pieces (8a/8b) crossing at least one semiconductor element of the plurality of semiconductor elements, and the plurality of lead electrode pieces are bonded to each other via third bonded portions (8c, 12). Regarding claim 2, Maeda further discloses: the third bonded portion has a bonding surface with the lead electrode piece in the lateral direction of the lead electrode, and the bonding surface is perpendicular to an upper surface of the lead electrode (Fig. 6) Regarding claim 3, Maeda further discloses: one of the adjacent lead electrode pieces has a concave portion (Fig. 5, 81), and an other has a convex portion (82), and the concave portion and the convex portion are engaged with each other and bonded via the third bonded portion. Regarding claim 7, Maeda further discloses: a base plate (2) to which the insulating substrate is bonded. Regarding claim 8, Maeda discloses a method of manufacturing a semiconductor device comprising: a first bonding material placing step of placing a first bonding material (9) on a circuit pattern provided on an insulating substrate at a position where a semiconductor element is to be mounted (Paragraph [0021]); a semiconductor element placing step of placing a plurality of semiconductor elements (10) on the first bonding material (Paragraph [0021]); a second bonding material placing step of placing a second bonding material (11) on each of the semiconductor elements; a lead electrode piece placing step of placing a plurality of lead electrode pieces composing the lead electrode on the second bonding material (Paragraph [0023]); a third bonding material placing step of placing a third bonding material (12) on the plurality of lead electrode pieces; and a bonding material heating step of heating the first bonding material, the second bonding material, and the third bonding material (Paragraph [0024]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 6 & 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (WO 2021/075016) in view of Shigimoto (Pre-Grant Publication 2021/0043598). Regarding claim 6, Maeda discloses all of the limitations of claim 1 (addressed above). Maead does not explicitly disclose an end portion of the at least one lead electrode piece of the plurality of lead electrode pieces is bonded to an external electrode via an external electrode bonded portion. However Shigimoto discloses a semiconductor device comprising: A lead electrode (Fig. 3, 6) wherein a end portion is bonded to an external electrode (7) via a bonded portion (9). It would have been obvious to those having ordinary skill in the art at the time of invention to bond an end of an lead electrode piece to an external electrode because it will ensure a secured bond between the end points with small residual stress to improve reliability of the device (Paragraph [0055) and will allow access to the lead electrode outside any sealant/encapsulation for electrical signals to and from the semiconductor elements. Regarding claim 6, Maeda discloses all of the limitations of claim 1 (addressed above). Maeda does not explicitly disclose in the bonding material heating step, heating at least one of the first bonding material, the second bonding material, and the third bonding material is performed as a separate step, and an assembly body is sequentially produced. However Shigimoto discloses a semiconductor device comprising: A first bonding and heating step to bond semiconductor elements (5) to base part (1) (Paragraph [0032]), a second bonding and heating step to bond lead electrode (6) to a surface of the semiconductor elements (5) (Paragraph [0034]), a third bonding and heating step to bond end portion of lead electrode (6) to end portion external lead (7) (Paragraph [0035]) wherein the bonding and heating steps are performed as separate steps. It would have been obvious to those having ordinary skill in the art at the time of invention to form the bonding heat step wherein at least one of the bonding materials is performed as a separate step because it will ensure a secure bond between parts of the semiconductor assembly prior to performing another bonding process. Allowable Subject Matter Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 4 is considered allowable because none of the prior art either alone or in combination discloses wherein one of the adjacent lead electrode pieces has a hook shape, and another has a shape that hooks the hook shape, and the hook shape and the shape that hooks are engaged with each other and bonded via the third bonded portion. Claim 5 is considered allowable because none of the prior art either alone or in combination discloses wherein the adjacent lead electrode pieces are connected so as rotate with each other and bonded to each other via the third bonded portion. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRANDON C FOX/Examiner, Art Unit 2818 /DAVID VU/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Jan 09, 2024
Application Filed
Mar 05, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
96%
With Interview (+10.0%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 800 resolved cases by this examiner. Grant probability derived from career allow rate.

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