Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on January 11, 2024, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Hatakeyama et al. (US 5972482 A) in view of Hiraoka et al. (US 20040191497 A1)
Regarding Claim 1 – Hatakeyama discloses a wiring board (Fig 5(h); 514) comprising: a first substrate (Fig 5(f); 511); a surface electrical conductor layer (Fig 5(e); 506/507); and a second substrate containing an organic material as an insulating base material (Figs 5(f-g); 509/510; Hatakeyama (Example 4) states “intermediate connecting members 509 and 510”, additionally Fig 4(a); Hatakeyama (Example 3) states “composite material consisting of aromatic polyamide… impregnated with thermosetting resin and epoxy resin was used”), wherein the first substrate, the surface electrical conductor layer, and the second substrate are laminated in this order (Figs 5(f-g); Hatakeyama (Example 4) states “511 was placed… between first intermediate connecting member 509 and second intermediate connecting member 510, and first metal foil 501 the second metal foil 502 were laminated… 511 and first and second metal foils 501 and 502 were adhered via intermediate connecting members 509 and 510 through heating and pressurization”), the surface electrical conductor layer is located on a surface of the first substrate (Fig 5(e); 506/507 on 511; see also Hatakeyama (Example 7) states “the copper foil layer was formed into circuit patterns… a double sided printed circuit board was produced”), the second substrate comprises a plurality of interlayer connection conductors (Figs 5(f-h); Hatakeyama (Example 4) states “As for intermediate connecting members 509 and 510, the uncured substrate material having closed voids manufactured in the method shown in FIGS. 4 (a) to (d) was used which was filled with the conductive paste in the through-hole and in the plurality of hollow-shaped parts formed on the inner wall of the through-hole” and Hatakeyama (Example 3) states “through-hole 405… filled with conductive paste 407… the metal foils are electrically connected via conductive paste 407”), the interlayer connection conductor extends in a thickness direction of the second substrate (Figs 4(c-e) Hatakeyama (Summary/ Example 3) states “a printed circuit board comprises a resin impregnate fiber sheet substrate with through-holes formed in the thickness direction”), the surface electrical conductor layer and the interlayer connection conductor are electrically connected to each other (Fig 5(g); Hatakeyama (Example 4) states “first metal foil 501 was electrically connected to second circuit pattern 506, and the second metal foil 502 was connected to third circuit pattern 507”).
Hatakeyama fails to disclose one end of the interlayer connection conductor is exposed from a surface of the second substrate; the insulating base material of the second substrate comprises a first region and a second region, the first region is located on the surface electrical conductor layer, the second region is located on the surface of the first substrate, and a density of the first region is higher than that of the density of the second region.
Hiraoka teaches one end of the interlayer connection conductor is exposed from a surface of the second substrate (Figs 1-2; Hiraoka [0076] states “exposed from the surface” And Hiraoka [0049] states “penetrates deep… thus forming vias” see also Hiraoka [0089] states “printing… on one major surface… form vias.” Thus, the printed end of the interlayer connection conductor is exposed at that surface at formation, providing the required exposed end); the insulating base material of the second substrate comprises a first region and a second region (Fig 2; 11a/11b/11; Hiraoka [0029] states “The fine porous surface 11a… and… the opposite coarse porous surface 11b, thus representing asymmetrical structure of the porous substrate 11” additionally Hiraoka [0035] states “the sheet-like porous substrate… asymmetrical structure where apertures of the first major surface have an average diameter and an average numerical aperture, at least one of which is smaller than that of the second major surface.”), the first region is located on the surface electrical conductor layer (Figs 1-2; 11a/12; Hiraoke [0028] states “a conductive portion 12 is formed on the fine porous surface 11a”), the second region is located on the surface of the first substrate (Fig 2; 11b; Hiraoka [0030] states “the coarse porous surface 11b… is employed as a surface to be press-contacted with the conductive portion 12 of a lower wiring member 10… making it possible to absorb the recessed/projected portions of the underlying wiring member 10”), and a density of the first region is higher than that of the density of the second region (Fig 2; 11a/11b; Hiraoka [0030] states “the fine porous surface 11a is relatively densified… the coarse porous surface 11b… is designed to have… average… aperture thereof are larger than those of the fine porous surface 11a”, Hiraoka [0046] states “An average numerical aperture of the fine porous surface… 5 to 40%” and Hiraoka [0047] states “An average numerical aperture of the coarse porous surface… 50 to 95%”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the wiring board of Hatakeyama with one end of the interlayer connection conductor is exposed from a surface of the second substrate; the insulating base material of the second substrate comprises a first region and a second region, the first region is located on the surface electrical conductor layer, the second region is located on the surface of the first substrate, and a density of the first region is higher than that of the density of the second region as taught by Hiraoka to get the benefit of obtaining direct surface access while maintaining through-thickness connectivity (Hiraoka [0049, 0089]) together with improved adhesion (Hiraoka [0031]).
Regarding Claim 2 – Hatakeyama in view of Hiraoka teaches the wiring board according to claim 1, comprising a cover electrical conductor layer located on a surface of the surface electrical conductor layer (Fig 2; conductive portion 12 on 11a; Hiraoka [0074] states “form a plated layer on the surface of the conductive portion by Ni--Au plating, tin plating, solder plating”).
Regarding Claim 3 – Hatakeyama in view of Hiraoka teaches the wiring board according to claim 1, wherein the interlayer connection conductor contains a resin component (Figs 2(c-f); Hatakeyama (Example 1) states “conductive paste 204 is composed of copper powder… and epoxy resin of non-solvent type as the binder resin” and “the binder component was pressed out between the conductive substances, thereby strengthening the binding”), and the resin component is located in an outer peripheral region of the interlayer connection conductor (Figs 2(d-f); Hatakeyama (Example 1) states “a part of binder resin 204a… had already penetrated into the side of aramid-epoxy sheet 202” and “binder component 204a… impregnated into aramid-epoxy sheet 202 cured or hardened” see also Fig 7(c); Hatakeyama (Example 6) states “the resin compound in the conductive paste impregnates into the base material side… Thus, a mixed layer 703c can be formed”) and forms a strip shape in the thickness direction of the second substrate (Fig 7(c); 703c continuous along 703; Hatakeyama (Example 6) quoted above; see also Figs 2(d-f); Hatakeyama (Example 1) quoted above).
Regarding Claim 4 – Hatakeyama in view of Hiraoka teaches the wiring board according to claim 3, wherein the interlayer connection conductor contains a metal particle (Fig 2(c); 204; Hatakeyama (Example 1) states “composed of copper powder with an average particulate diameter of 2 μm… and epoxy resin of non-solvent type as the binder resin… with the content of the copper powder set at 85 wt %”), in a plan view of the second substrate, the interlayer connection conductor comprises the outer peripheral region comprising an outer edge of the interlayer connection conductor, and an inner region passing through a central axis of the interlayer connection conductor and located on an inner side of the outer peripheral region (Figs 2(b-c); 203/204; Hatakeyama (Example 1) states “through-holes 203 of 200 μm in diameter were formed…” and “through-holes 203 were filled with conductive paste 204” cylindrical , filled via - inherent outer peripheral region at the wall/edge and an inner region through the axis in plan view), and a volume ratio of the metal particle in the outer peripheral region is greater than a volume ratio of the metal particle in the inner region (Figs 2(d-f); Hatakeyama (Example 1) states “a part of binder resin 204a… had already penetrated into the side of aramid-epoxy sheet 202” and “the binder component was pressed out between the conductive substances, thereby strengthening the binding… the content of the conductive substance contained in the conductive paste 204 raised up to 92.5 wt %”; see also Fig 7(c); Hatakeyama (Example 6) states “the resin compound in the conductive paste impregnates into the base material side… Thus, a mixed layer 703c can be formed”).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Hatakeyama et al. (US 5972482 A) in view of Hiraoka et al. (US 20040191497 A1) in further view of Adachi (US 10257923 B2)
Regarding Claim 5 – Hatakeyama in view of Hiraoka teaches the wiring board according to claim 1, wherein in the interlayer connection conductor (Hatakeyama, Figs 4(c-e); 405/407; Figs 5(f-h); 509/510; Hatakeyama (Example 3) states “the metal foils are electrically connected via conductive paste 407”), but fail to disclose a diameter of a portion close to the surface of the second substrate is smaller than a diameter of a portion located at a center in the thickness direction of the second substrate.
Adachi teaches a diameter of a portion close to the surface of the second substrate is smaller than a diameter of a portion located at a center in the thickness direction of the second substrate (Figs 4A-4B; Adachi (Detailed Description para 21) states “the interlayer connection conductors 310 and 320 preferably have… an inverted circular cone shape… the diameters… change along the thickness direction” and further (para 26) states “surfaces with a larger diameter may preferably be connected to each other”).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have provided the wiring board of Hatakeyama in view of Hiraoka with a diameter of a portion close to the surface of the second substrate is smaller than a diameter of a portion located at a center in the thickness direction of the second substrate as taught by Adachi because Adachi (Detailed Description para 12) states “With this configuration, the difference in density between the first portion and the second portion is significantly reduced, and warpage is further easily reduced” and (para 23) states “substrate… is able to be more surely mounted on the printed wiring board”.
Regarding Claim 6 – Hatakeyama in view of Hiraoka and in further view of Adachi teaches the wiring board according to claim 5, wherein in the interlayer connection conductor (Hatakeyama, Fig 5(g); 509/510 abutting the first substrate’s surface electrical conductor layer 506/507 on 511), a diameter of a portion close to the surface electrical conductor layer is smaller than the diameter of the portion located at the center in the thickness direction of the second substrate (Adachi, Figs 4A-4B; 310/320; para 21 quoted above).
Conclusion
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/ADITYA SHARMA/ Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/ Supervisory Patent Examiner, Art Unit 2847