DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on 06/18/2026 has been entered. Claims 1, 4-6, 8-11, and 16-19 remain pending in the application. Claims 2-3, 7, 12-15 and 20 have been cancelled. Applicant’s amendments have overcome each and every 112(b) rejections previously set forth in the Non-Final Office Action mailed on 03/19/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 10, 11, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shih et al., (United States Patent Number, US 10,049,928 B2) hereinafter referenced as Shih, in view of Juang et al., (United States Patent Application Publication Number, US 2023/0411171 A1), hereinafter referenced as Juang.
Regarding claim 1, Shih teaches a method for manufacturing an encapsulation substrate, comprising: providing an initial substrate, wherein the initial substrate comprises a first surface and a second surface which are oppositely arranged along a thickness direction of the initial substrate (Fig.1A, element #10, first surface the one in contact with element #18, the second surface is the one opposite to the first surface) and the initial substrate comprises a semiconductor or a dielectric material such as a silicon oxide (column 2, rows 40-44). Shih does not teach wherein the initial substrate comprises a glass substrate (Note that silicon oxide is a general terms for silicon dioxide which is the main ingredient of glass). Juang teaches a method for manufacturing an encapsulation substrate, comprising: providing an initial substrate, wherein the initial substrate comprises a first surface and a second surface which are oppositely arranged along a thickness direction of the initial substrate, and the initial substrate comprises a glass substrate (Fig.1, element #100, first surface is top surface, elements #S1, and second surface is the bottom surface, element #S2, is made of glass, paragraph [0011], rows 1-3). Note that Juang also teaches forming blind holes in the glass substrate and connection electrodes in the blind hole (Fig.2), forming a first signal trace on the first surface connected to the first connection electrode (Fig.7); fixing an carrier substrate on a side of the first signal trace away from the first surface (Fig.8, element #110); thinning the initial substrate from a side of the second surface to form a dielectric substrate comprising a through hole and to expose the first connection electrode (Fig.9) and forming the a second signal trace on a side of the dielectric substrate away from the first signal trace (Fig.10).
Thus, both references Shih and Juang teach an initial substrate that can be used for the same purpose, as an interposer. A person skilled in the art before the effective filing date of the claimed invention would have recognized that the substrate disclosed by Shih could have been replaced for the glass substrate disclosed by Juang because both serve the same purpose of providing an initial substrate for an interposer. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an initial substrate for an interposer. As compared to Shih which teaches the substrate may be a semiconductor substrate, the glass substrate taught by Juang eliminates the need for a dielectric liner to electrically isolate the connection electrode from the substrate, thus reducing process steps which may reduce yield.
Shih further teaches processing the initial substrate to form a blind hole extending through a part of the initial substrate in the thickness direction of the initial substrate, wherein a first opening of the blind hole extends through the first surface (Fig.1A, holes corresponding to elements #20 have an opening extending through the first surface); forming a first connection electrode in the blind hole (Fig.1A, element #20), and forming a first signal trace on the first surface (Fig.1D, formed by elements #12 and #30), wherein one end of the first signal trace is electrically connected to the first connection electrode (Fig1D, bottom surface of elements #12 is electrically connected to element #20); fixing a carrier substrate on a side of the first signal trace away from the first trace (Fig.1E, element #36), thinning the initial substrate from a side of the second surface to form a dielectric substrate comprising a through hole and to expose the first connection electrode (Fig.1F, column 3, rows 40-43); removing the carrier substrate (Fig.1G, element #36 is removed) forming a second signal trace layer on a side of the dielectric substrate away from the first signal trace (Fig.1F, elements #37), fixing an auxiliary substrate on a side of the second signal trace away from the dielectric substrate (column 3, rows 62-64); mounting a chip on a side of the first signal trace away from the dielectric substrate, wherein the chip is electrically connected to the first signal trace (Fig.1G, chip element #44 is mounted of a side of element #30, and electrically connected to them through element #46A, column 4, rows 6-9); forming an encapsulation layer on a side of the chip away from the dielectric substrate (Fig.2A, element #54); and removing the auxiliary substrate (Fig.1G, PCB, element #50 is connected to bumps #38, which implies the auxiliary substrate was removed), wherein the first signal trace is configured to be electrically connected to a chip and the second signal trace is configured to be electrically connected to a printed cricoid board (Fig.1G, elements #30 are connected to a chip, element #44 and elements #37 are connected to a PCB, element #50).
As noted above, Juang also teaches processing the glass substrate to form a blind hole extending through a part of the initial substrate in the thickness direction of the initial substrate, wherein a first opening of the blind hole extends through the first surface (Fig.1, elements #103); forming a first connection electrode in the blind hole (Fig.2, element #106), and forming a first signal trace on the first surface, wherein one end of the first signal trace is electrically connected to the first connection electrode (Fig.7, signal trace formed by elements #MF11, #SL12, #MF12, #SL13 #MF13, #SL14 and #MF14); fixing an carrier substrate on a side of the first signal trace away from the first surface (Fig.8, element #110); thinning the initial substrate from a side of the second surface to form a dielectric substrate comprising a through hole and to expose the first connection electrode (Fig.9, substrate #100 is thinned and the electrode is exposed); removing the carrier substrate (Fig.12) forming a second signal trace on a side of the dielectric substrate away from the first signal trace (Fig.10, trace formed by elements #SL21, #MF21, #SL22, #MF22, #SL23 and #MF23). Processing the glass substrate disclosed by Juang using above limitations of the claimed method, and in a similar way as the substrate disclosed by Shih, further emphasizes why a person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the substrate disclosed by Shih could have been replaced for the glass substrate disclosed by Juang with predictable results.
Regarding claim 4, the combination of Shih and Juang teaches the method of claim 1 as set forth in the obviousness rejection. Shih further teaches the method according to claim 1, wherein the chip is electrically connected to the first signal trace by soldering (Fig.1G, elements #46a are solder bumps, column 3, rows 65-67).
Regarding claim 5, the combination of Shih and Juang teaches the method of claim 1 as set forth in the obviousness rejection. Shih teaches an auxiliary substrate fixed to the side of the second signal trace away from the dielectric substrate (column 3, rows 62-63). Shih does not explicitly teach how the auxiliary substrate is fixed to the side of the second signal trace. However, Shih teaches the carrier substrate is fixed with adhesive ( Fig.1F, carrier element #36 is fixed with adhesive, element #39). Therefore, it would have been obvious to one ordinary skilled in the art to also use an adhesive in order to fix the auxiliary carrier. This allows one to perform the same process as the one used when fixing the first carrier substrate, which simplifies the manufacturing process.
Regarding claim 6, the combination of Shih and Juang teaches the method of claim 1 as set forth in the obviousness rejection. Shih further teaches the method according to claim 1, wherein the carrier substrate is fixed to the side of the first signal trace away from the first surface through a second adhesive layer (Fig.1F, carrier, element #36 is fixed through adhesive layer, element #39, column 3, rows 37-40).
Regarding claim 10, the combination of Shih and Juang teaches the method of claim 1 as set forth in the obviousness rejection. Shih further teaches the method according to claim 1, wherein one end of the first signal trace is connected to the first connection electrode, and a first connection pad is formed on a side of the other end of the first signal trace away from the dielectric substrate (Fig.1D, element #32, column 3, rows 26-28). Juang further teaches one end of the second signal trace is connected to the first connection electrode, and a second connection pad is formed on a side of the other end of the second signal trace away from the dielectric substrate (Fig.10, the second trace end with pad element #MF23).It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention, to incorporate the teachings of Juang and disclose one end of the second signal trace is connected to the first connection electrode, and a second connection pad is formed on a side of the other end of the second signal trace away from the dielectric substrate. As disclosed by Juang, the second trace can be part of a redistribution layer (Fig.10, element #112) which allows rearranging the connection points of the substrate, in order to match with the position of pads of chips or printed circuit boards, while the pad facilitates the electrical connection and allows the power/signal to be transmitted to or from the connected chips or printed circuit boards.
Regarding claim 11, the combination of Shih and Juang teaches the method of claim 1 as set forth in the obviousness rejection. Shih does not teach the method according to claim 1, wherein the first connection electrode is formed through an electroplating process or an electroless plating process. Juang teaches the method according to claim 1, wherein the first connection electrode is formed through an electroplating process or an electroless plating process (paragraph [0013], rows 3-5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Juang and disclose wherein the first connection electrode is formed through an electroplating process or an electroless plating process. Electroplating can produce void free uniform metal fills and offers compatibility with high density interconnect technology.
Regarding claim 16, the combination of Shih and Juang teaches the method of claim 1 as set forth in the obviousness rejection. Shih further teaches a method for manufacturing a functional substrate comprising the method for manufacturing an encapsulation substrate according to claim 1 (Fig.3C shows a functional substrate).
Regarding claim 18, the combination of Shih and Juang teaches the method of claims 1 and 16 as set forth in the obviousness rejection. Shih further teaches the method according to claim 16 ,wherein the second signal trace is configured to be electrically connected to the printed circuit board by soldering (Fig.1G, the second signal trace is connected through elements #38 which are made of solder, column 3, rows 49-51).
Claims 8, 9, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., (United States Patent Application Publication Number, US 2020/0152563 A1) hereinafter referenced as Chen_563, in view of Juang.
Regarding claim 8, Chen_563 teaches a method for manufacturing an encapsulation substrate, comprising: providing an initial substrate, wherein the initial substrate comprises a first surface and a second surface which are oppositely arranged along a thickness direction of the initial substrate (Fig.1A, element #102, first surface is top surface and second surface is bottom surface), and the initial substrate comprises a semiconductor substrate (paragraph [0024]).
Chen_563 does not teach the initial substrate comprises a glass substrate. Juang teaches a method for manufacturing an encapsulation substrate, comprising: providing an initial substrate, wherein the initial substrate comprises a first surface and a second surface which are oppositely arranged along a thickness direction of the initial substrate, and the initial substrate comprises a glass substrate (Fig.1, element #100, first surface is top surface, elements #S1, and second surface is the bottom surface, element #S2, is made of glass, paragraph [0011], rows 1-3). Note that Juang also teaches forming blind holes in the glass substrate and connection electrodes in the blind hole (Fig.2), forming a first signal trace on the first surface connected to the first connection electrode (Fig.7); fixing an carrier substrate on a side of the first signal trace away from the first surface (Fig.8, element #110); thinning the initial substrate from a side of the second surface to form a dielectric substrate comprising a through hole and to expose the first connection electrode (Fig.9) and forming the a second signal trace on a side of the dielectric substrate away from the first signal trace (Fig.10).
Thus, both references Chen_563 and Juang teach an initial substrate that can be used for the same purpose, as an interposer. A person skilled in the art before the effective filing date of the claimed invention would have recognized that the substrate disclosed by Shih could have been replaced for the glass substrate disclosed by Juang because both serve the same purpose of providing an initial substrate for an interposer. Furthermore, a person skilled in the art would have been able to carry out the substitution. Finally, the substitution achieves the predictable result of providing an initial substrate for an interposer. As compared to Shih which teaches the substrate may be a semiconductor substrate, the glass substrate taught by Juang eliminates the need for a dielectric liner to electrically isolate the connection electrode from the substrate, thus reducing process steps which may reduce yield.
Chen_563 further teaches processing the initial substrate to form a blind hole extending through a part of the initial substrate in the thickness direction of the initial substrate, wherein a first opening of the blind hole extends through the first surface (Fig.1A, element #104-1 extend through the top surface of element #102); forming a first connection electrode in the blind hole (paragraph [0027], rows 1-3), and forming a first signal trace on the first surface, wherein one end of the first signal trace is electrically connected to the first connection electrode (Fig.2B, element #130 contains first signal traces connected to element #104, paragraph [0035], rows 4-5); fixing an auxiliary substrate on a side of the first signal trace away from the first surface (Fig.8A, element #510 is fixed using adhesive, element #501); thinning the initial substrate from a side of the second surface to form a dielectric substrate comprising a through hole and to expose the first connection electrode (Fig.8C, paragraph [0087], rows 4-10); forming a second signal trace on a side of the dielectric substrate away from the first signal trace (Fig.8D, element #811 contains signal traces, paragraph [0088], rows 1-6), mounting a chip on a side of the second signal trace away from the dielectric substrate, wherein the chip is electrically connected to the second signal trace (Fig.8E, chips, element #504 and #506 are mounted on the second side and electrically connected through elements #824); and removing the auxiliary substrate (Fig.8F, element #510 is removed), wherein the second signal trace is configured to be electrically connected to the chip, and the first signal trace is configured to be electrically connected to a printed circuit board (the first and second signal traces end with bond pads, Fig.2B and Fig.8D respectively, and therefore are configured to be connected to a chip and a PCB).
As noted above, Juang also teaches processing the glass substrate to form a blind hole extending through a part of the initial substrate in the thickness direction of the initial substrate, wherein a first opening of the blind hole extends through the first surface (Fig.1, elements #103); forming a first connection electrode in the blind hole (Fig.2, element #106), and forming a first signal trace on the first surface, wherein one end of the first signal trace is electrically connected to the first connection electrode (Fig.7, signal trace formed by elements #MF11, #SL12, #MF12, #SL13 #MF13, #SL14 and #MF14); fixing an auxiliary substrate on a side of the first signal trace away from the first surface (Fig.8, element #110); thinning the initial substrate from a side of the second surface to form a dielectric substrate comprising a through hole and to expose the first connection electrode (Fig.9, substrate #100 is thinned and the electrode is exposed); removing the auxiliary substrate (Fig.12) forming a second signal trace on a side of the dielectric substrate away from the first signal trace (Fig.10, trace formed by elements #SL21, #MF21, #SL22, #MF22, #SL23 and #MF23). Processing the glass substrate disclosed by Juang using above limitations of the claimed method, and in a similar way as the substrate disclosed by Chen_563, further emphasizes why a person skilled in the art, before the effective filing date of the claimed invention, would have recognized that the substrate disclosed by Chen_563 could have been replaced for the glass substrate disclosed by Juang with predictable results.
Regarding claim 9, the combination of Chen_563 and Juang teaches the method of claim 8 as set forth in the obviousness rejection. Chen_563 further teaches the method according to claim 8, wherein the auxiliary substrate is fixed to a side of the first signal trace away from the first surface through a first adhesive layer (Fig.8A, substrate, element #510 is fixed to the first signal trace using adhesive, element #501).
Regarding claim 17, the combination of Chen_563 and Juang teaches the method of claim 8 as set forth in the obviousness rejection. Chen_563 further teaches a method for manufacturing a functional substrate, comprising the method for manufacturing an encapsulation substrate according to claim 8 (Fig.8F shows a functional substrate).
Regarding claim 19, the combination of Chen_563 and Juang teaches the method of claims 8 and 17 as set forth in the obviousness rejection. Chen_563 further teaches the method according to claim 17, wherein the first signal trace is configured to be electrically connected to the printed circuit board by soldering (Fig.1D the first signal trace is configured to connect through elements #326 which are similar to elements #126, made of solder, paragraph [0046] and paragraph [0031], rows 23-24) .
Response to Arguments
Applicant’s arguments filed on 06/28/2026 have been fully considered but they
are not persuasive. Applicant does not make any persuasive arguments as to why the combination of Shih and Shen used for the rejection of claims 1 and 8, and the combination of Shih, Shen and Chen_456 used for the rejection of claims 2-6, in the Non-final Office action filed on 03/19/2026, is not obvious. On page 10 of the Applicant Arguments/Remark filed on 06/18/2026, the applicant states that “only Shen has disclosed a solution regarding a glass substrate” and on page 11 that “the other cited references never mentioned how to form an interconnection between two opposite surfaces of the glass substrate”. The reference of Juang used for the rejection of claims 1 and 8 in this Final Office action, and the reference of Jeng, which is made of record but not relied upon, both disclose solutions for making an interconnection between opposite surfaces of a glass substrate. Therefore, applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference as applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jeng et al. (United States Patent Application Publication Number US 2022/0045016 A1) teaches a method for manufacturing an encapsulation substrate, comprising: providing an initial substrate, wherein the initial substrate comprises a first surface and a second surface which are oppositely arranged along a thickness direction of the initial substrate, and the initial substrate comprises a glass or a semiconductor substrate (Fig.1A, element #1-0, paragraph [0028], rows 1-10); processing the initial substrate to form a blind hole extending through a part of the initial substrate in the thickness direction of the initial substrate, wherein a first opening of the blind hole extends through the first surface (Fig.1A); forming a first connection electrode in the blind hole, and forming a first signal trace on the first surface, wherein one end of the first signal trace is electrically connected to the first connection electrode (Fig.1B-1D); fixing a carrier substrate on a side of the first signal trace away from the first trace (Fig.1G, element #134) thinning the initial substrate from a side of the second surface to form a dielectric substrate comprising a through hole and to expose the first connection electrode (Fig.1G); removing the carrier substrate (Fig.1I); forming a second signal trace on a side of the dielectric substrate away from the first signal trace (Fig. 1I, element #138), fixing an auxiliary substrate on a side of the second signal trace away from the dielectric substrate (Fig. 1I, element #142, the tape is supporting the structure and therefore can be considered a substrate); mounting a chip on a side of the first signal trace away from the dielectric substrate, wherein the chip is electrically connected to the first signal trace; (Fig.1I, elements #124) forming an encapsulation layer on a side of the chip away from the dielectric substrate (Fig.1I, elements #132); and removing the auxiliary substrate (Fig.1J, element #142 is removed), wherein the first signal trace is configured to be electrically connected to a chip, and the second signal trace is configured to be electrically connected to a printed circuit board (Fig.1J they are configured to be electrically connected through elements #120e and #138) .
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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