Prosecution Insights
Last updated: October 01, 2026
Application No. 18/580,580

SANDWICHED MULTI-LAYER STRUCTURE FOR COOLING HIGH POWER ELECTRONICS

Final Rejection §102§103
Filed
Jan 18, 2024
Priority
Aug 18, 2021 — provisional 63/234,602 +1 more
Examiner
ZABEL, ANDREW JOHN
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Tesla Inc.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
8m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
32 granted / 38 resolved
+16.2% vs TC avg
Strong +24% interview lift
Without
With
+24.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
37 currently pending
Career history
79
Total Applications
across all art units

Statute-Specific Performance

§103
71.6%
+31.6% vs TC avg
§102
23.2%
-16.8% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 38 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments In response to the applicants arguments, filed 06/18/2026, with regards to Kitami et al (US 20120228757) on pages 5 and 6 with regards to the definition of “radiator” as expressed in Kitami et al as being one of heatsink, liquid cooling element or cold plate. The office finds the argument unpersuasive, a radiator, as disclosed by Kitami et al, functionally and structurally is the same as a heatsink, cold plate or liquid cooling element, and comprise the same structure and function. One particular definition of a radiator is a liquid cooling element, thus under the broadest reasonable interpretation of the term “radiator” as disclosed in Kitami et al, it would be reasonable to a person of ordinary skill in the art to comprehend such a term as a liquid cooling element, or even a heatsink [which by definition is a structural element that takes heat from another element to cool said element]. The rejection of claims 1 and 18 are maintained. With regards to the arguments on pages 7 and 8 with regards to the combination of Kitami et al with Yu et al, it would be obvious to one of ordinary skill in the art to utilize the structure of Kitami et al to allow more functionality than just an inverter, by incorporating different types of electronic layers that are cooled, such as a processing or control electronics layer. This allows the combination to perform more functions than just Kitami et al can perform, allowing a single device to be more “versatile” in its performance. Also note that since the two references are in the same field of endeavor, which is the requirement for the combination of the elements, it would be obvious to one of ordinary skill in the art to look in the same field of endeavor for ideas on how to improve a device to be more versatile. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 12, 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kitami et al (US 20120228757 A1). Kitami et al teaches [claim 1] A computing assembly comprising: a first cooling system (paragraphs 0046-0047, figure 3, element 10 is the computing assembly comprising a first cooling system [element 41] on the top of the figure [just above element 46]), a first electronics layer having a first surface and a second surface, wherein the first surface is in thermal communication with the first cooling system (paragraphs 0047-0048, where elements 26, 32, and 31 comprise the first electronics layer and the top surface [top of element 26] in thermal communication with the first cooling system [element 41], and a second surface [bottom of element 31]); a second cooling system in thermal communication with the second surface of the first electronics layer (paragraphs 0047-0048, figure 3, where elements 56 and 60 comprise the second cooling system and in thermal communication with the second surface of the first electronics layer [bottom surface of element 31]) and a second electronics layer having a third surface and a fourth surface, wherein the third surface is in thermal communication with the second cooling system (paragraph 0047-0048, figure 3, where elements 36 and 27 comprise the second electronics layer with a third surface [top surface of element 36] and a fourth surface [bottom surface of element 27], where the third surface is in communication with the second cooling system [elements 60 and 56]), wherein a type of the first cooling system and a type of the second cooling system comprise one or more of a cold plate, a heatsink, and a liquid cooling block (paragraph 0047, figure 3, where element 41 the first cooling structure, and is called a “radiator” which per the definition of “radiator” acts either like a liquid cooling block or a heatsink depending on the specific usage). [claim 2] The computing assembly of wherein the first cooling system is disposed on top of the first electronics layer (paragraphs 0046-0047, figure 3, where the first cooling system [element 41] is disposed on a top surface of the first electronics layer [elements 26 and 31]), wherein the first electronics layer is disposed on top of the second cooling system and wherein the second cooling system is disposed on top of the second electronics layer (figure 3, paragraphs 0046-0048, where the first electronics layer [elements 31 and 26] is disposed on the second cooling system [elements 60 and 56] and said cooling system is disposed on the second electronics layer [elements 36 and 27]), wherein a type of the first cooling system and a type of the second cooling system comprise one or more of a cold plate, a heatsink, and a liquid cooling block (paragraph 0047, figure 3, where element 41 the first cooling structure, and is called a “radiator” which per the definition of “radiator” acts either like a liquid cooling block or a heatsink depending on the specific usage). [claim 3] The computing assembly of Claim 1, further comprising: a third cooling system (paragraph 0054, figure 3, element 42 is the third cooling system); and a third electronics layer having a fifth surface and sixth surface, wherein the fifth surface is in thermal communication with the third cooling system (paragraphs 0046-0048, where elements 26 and 31 situated directly below element 42 is the third electronics layer where the fifth surface is the top of element 26 and the sixth surface is the bottom of element 31, and the fifth surface is in thermal communication with the third cooling system [element 26 below element 42 is in thermal communication with element 42]), wherein and the fourth surface is in thermal communication with the third cooling system (figure 3, paragraph 0047 and 0054, where the fourth surface [bottom of element 27] is in thermal communication of element 42 [the third cooling system]). [claim 4] The computing assembly of Claim 1, wherein the first electronics layer is in electrical communication with the second electronics layer (paragraphs 0049-0051, figures 2 and 3, where the first electronics layer [elements 26 and 31] are in communication with line PL2 of figure 2, and the second electronics layer [elements 27 and 36] are in communication with line PL3 of figure 2, where PL2 and PL3 are electrically connected through element C2 and the other transistor circuits [Q3-Q8 and D3-D8]). [claim 12] The computing assembly of Claim 1, wherein the type of the first cooling system is different from the type of the second cooling system (paragraphs 0047, and 0061, where element 41 and element 60 are the first and second cooling systems and are different types of cooling systems). [claim 18] A method for cooling an electronic assembly comprising: mounting a first cooling layer on top of and in thermal communication with a first electronics layer (paragraphs 0047-0048, figure 3, where elements 26, 32, and 31 comprise the first electronics layer and the top surface [top of element 26] in thermal communication with the first cooling system [element 41], and a second surface [bottom of element 31]); mounting a first electronics layer on top of and in thermal communication with a second cooling system (paragraphs 0047-0048, figure 3, where elements 56 and 60 comprise the second cooling system and in thermal communication with the second surface of the first electronics layer [bottom surface of element 31], where the first electronics layer is mounted on top of the second cooling system); and mounting a second cooling system on top of and in thermal communication with a second electronics layer (paragraph 0047-0048, figure 3, where elements 36 and 27 comprise the second electronics layer with a surface [top surface of element 36] and a fourth surface [bottom surface of element 27], where the surface is in thermal communication with the second cooling system [elements 60 and 56]), wherein a type of the first cooling system and a type of the second cooling system comprise one or more of a cold plate, a heatsink, and a liquid cooling block (paragraph 0047, figure 3, where element 41 the first cooling structure, and is called a “radiator” which per the definition of “radiator” acts either like a liquid cooling block or a heatsink depending on the specific usage). [claim 19] The method of claim 18, further comprising: outputting heat vertically from the first electronics layer to the first cooling system (paragraphs 0047-0048, figure 3, where elements 26, 32, and 31 comprise the first electronics layer and the top surface [top of element 26] in thermal communication with the first cooling system [element 41], where the heat is dissipated vertically to the first cooling system); outputting heat vertically from the first electronics layer to the second cooling system; and outputting heat vertically from the second electronics layer to the second cooling system (paragraph 0047-0048, figure 3, where elements 36 and 27 comprise the second electronics layer with a surface [top surface of element 36] and a surface [bottom surface of element 27], where the surface is in thermal communication with the second cooling system [elements 60 and 56], and the heat dissipated vertically through the electronics layer to the second cooling system). [claim 20] The method of claim 18, further comprising: providing power vertically from the second electronics layer to the first electronics layer (paragraphs 0049-0051, figures 2 and 3, where the first electronics layer [elements 26 and 31] are in communication with line PL2 of figure 2, and the second electronics layer [elements 27 and 36] are in communication with line PL3 of figure 2, where PL2 and PL3 are electrically connected through element C2 and the other transistor circuits [Q3-Q8 and D3-D8]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5-6, 8-9, 11, 13-17, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kitami et al (US 20120228757 A1) in view of Yu et al (US 20190304959 A1). Kitami et al teaches [claim 21] A computing assembly comprising: a first cooling system (paragraphs 0046-0047, figure 3, element 10 is the computing assembly comprising a first cooling system [element 41] on the top of the figure [just above element 46]); a first electronics layer in thermal communication with the first cooling system (paragraphs 0047-0048, where elements 26, 32, and 31 comprise the layer where the first electronics layer is situated and the in thermal communication with the first cooling system [element 41]): a second cooling system in thermal communication with the first electronics layer (paragraphs 0047-0048, figure 3, where elements 56 and 60 comprise the second cooling system and in thermal communication with the the first electronics layer [bottom surface of element 31]); a second electronics layer in thermal communication with the second cooling system (paragraph 0047-0048, figure 3, where elements 36 and 27 comprise the layer which the second electronics layer is situated, where it is in communication with the second cooling system [elements 60 and 56]). a third cooling system in thermal communication with the second electronics layer (paragraph 0054, figure 3, element 42 is the third cooling system); and a third electronics layer in thermal communication with the third cooling system (paragraphs 0046-0048, where elements 26 and 31 situated directly below element 42 is the layer where the third electronics layer is situated and is in thermal communication with the third cooling system [element 26 below element 42 is in thermal communication with element 42]), wherein the second electronics layer comprises a power delivery layer (paragraphs 0050-0051, figures 2-3, where the second electronics layer comprises element 36 which relates to the transistor/diode circuits of figure 2 connected to PL3 [power-line 3] which delivers power to the motor [element 100 of figure 2], thus consisting of a power delivery layer). However, Kitami et al does not specifically disclose [claim 21] wherein the first electronics layer comprises a processing electronics layer, and wherein the third electronics layer comprises a control electronics layer. However, Yu et al teaches [claim 21] wherein the first electronics layer comprises a processing electronics layer (paragraph 0017, where element 100 consists of the first electronics layer replacing the first electronics layer of Kitami et al and consists of device dies that process information [such as logic dies]), and wherein the third electronics layer comprises a control electronics layer (paragraph 0017, figure 1, element 200 consists of the third electronics layer replacing the third electronics layer of Kitami et al, and consists of a control electronics layer [such as a logic die, which controls devices via logic]). It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kitami et al to include the teaches of Yu et al in order to use different semiconductor circuits for the electronics layers to allow for more versatility from the electronic device. Regarding claims 5-6, 8-9, 11, and 13-17, Kitami et al teaches all of the limitations of the parent claim, claim 1, and further teaches [claim 6] the second electronics layer comprises a power delivery module (paragraph 0050-0051, figures 2-3, where element 36 in the second electronics layer is the transistor/diode circuits of figure connected to PL3 [power-line 3] where the circuit delivers power to the motor, thus comprising a power deliver module). However, Kitami et al does not specifically disclose [claim 5] The computing assembly of claim 1, wherein the first electronics layer comprises a system on wafer layer. [claim 6] The computing assembly of claim 1, wherein the first electronics layer comprises an array of integrated circuit dies, and wherein [the second electronics layer comprises] an array [of power delivery modules]. [claim 8] The computing assembly of claim 6, wherein a number of integrated circuit dies in the first electronics layer is equal to a number of power delivery modules in the second electronics layer, and wherein each integrated circuit die is in electrical communication with only one power delivery module. [claim 9] The computing assembly of claim 6, wherein power is delivered vertically from the second electronics layer to the first electronics layer, and wherein the integrated circuit dies of the array of integrated circuit dies are in electronic communication with each other in a plane that is orthogonal to the power delivery. [claim 11] The computing assembly of claim 1, wherein the type of the first cooling system is the same as the type of the second cooling system. [claim 13] The computing assembly of claim 11, wherein the first cooling system comprises a first liquid cooling block and the second cooling system comprises a second liquid cooling block. [claim 14] The computing assembly of claim 13, wherein the first liquid cooling block is configured to receive a first coolant, and wherein the second liquid cooling block is configured to receive a second coolant. [claim 15] The computing assembly of claim14, wherein the first coolant and the second coolant comprise one or more of water, propylene glycol, ethylene glycol, or any combination thereof. [claim 16] The computing assembly of claim 14, wherein the first coolant is the same as the second coolant. [claim 17] The computing assembly of Claim 14, wherein the first coolant is different from the second coolant. However, Yu et al teaches [claim 5] The computing assembly of claim 1, wherein the first electronics layer comprises a system on wafer layer (paragraph 0017, figure 1, where element 100 replaces the first electronics layer and can contain system on a chip packages on the wafer). [claim 6] The computing assembly of claim 1, wherein the first electronics layer comprises an array of integrated circuit dies, [and wherein the second electronics layer comprises] an array [of power delivery module]s (paragraph 0017, figure 1, where the first electronics layer is element 100 and comprises an array of circuit dies [element 102], and the second electronics layer is element 200 and contains an array of die where the power delivery module portion is read into it from Kitami et al as the circuitry on the die). [claim 8] The computing assembly of claim 6, wherein a number of integrated circuit dies in the first electronics layer is equal to a number of power delivery modules in the second electronics layer (paragraph 0017, figure 1, where the first electronics layer [element 100] and the second electronics layer [element 200] has the same number of die [5 die]), and wherein each integrated circuit die is in electrical communication with only one power delivery module (paragraph 0017, figure 1, where the connective portions [element 108] connect each die directly above it and below it to the respective die above/below it). [claim 9] The computing assembly of claim 6, wherein power is delivered vertically from the second electronics layer to the first electronics layer, and wherein the integrated circuit dies of the array of integrated circuit dies are in electronic communication with each other in a plane that is orthogonal to the power delivery (paragraph 0017, figure 1, where the first electronics layer [element 100] is connected to the second electronics layer [element 200] through a vertical connection and orthogonal to the array of power deliver module [element 200 read into from Kitami et al], thus power is delivered vertically from element 200 to element 100). [claim 11] The computing assembly of claim 10, wherein the type of the first cooling system is the same as the type of the second cooling system (paragraph 0037, figure 13, where the first cooling system [element 32] is the same type of cooling system as the second cooling system [element 36], both are liquid coolant systems with fins). [claim 13] The computing assembly of claim 11, wherein the first cooling system comprises a first liquid cooling block and the second cooling system comprises a second liquid cooling block (paragraph 0037, figure 13, where the first cooling system [element 32] is the same type of cooling system as the second cooling system [element 36], both are liquid coolant systems with fins, thus both are liquid cooling blocks). [claim 14] The computing assembly of claim 13, wherein the first liquid cooling block is configured to receive a first coolant, and wherein the second liquid cooling block is configured to receive a second coolant (paragraphs 0033 and 0037, figure 13, where the first cooling system [element 32] is the same type of cooling system as the second cooling system [element 36], both are liquid coolant systems with fins and both may be filled with water, oil or cool air). [claim 15] The computing assembly of claim14, wherein the first coolant and the second coolant comprise one or more of water, propylene glycol, ethylene glycol, or any combination thereof (paragraph 0033, figure 13, where elements 32 and 36 can be filled with water, oil or air, in the present case water). [claim 16] The computing assembly of claim 14, wherein the first coolant is the same as the second coolant (paragraphs 0033 and 0037, figure 13, where elements 32 and 36 [first and second cooling blaocks] may contain the same coolant, that of water, oil or cool air). [claim 17] The computing assembly of Claim 14, wherein the first coolant is different from the second coolant (paragraphs 0033 and 0037, figure 13, where elements 32 and 36 [first and second cooling blocks] may be filled each with water, oil or cool air, and thus in a specific application one may be filled with water and the other with oil, being different coolants). It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kitami et al to include the teaches of Yu et al in order to use different semiconductor circuits and coolants for the electronics layers and coolant layers to allow for more versatility from the electronic device. Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kitami et al (US 20120228757 A1) and Yu et al (US 20190304959 A1) in further view of Xiong et al (US 20200113059). Kitami et al as modified teaches all of the limitations of the parent claim, claim 6, but does not specifically disclose [claim 7] The computing assembly of claim 6, wherein each power delivery module of the array of power delivery modules comprises a voltage regulating module. However, Xiong et al does teach [claim 7] The computing assembly of claim 6, wherein each power delivery module of the array of power delivery modules comprises a voltage regulating module (paragraph 0031, figure 2A, where the power deliver modules contain a voltage regulator module). It would have been obvious to one of ordinary skill in the art at the time of filing to have modified the teachings of Kitami et al as modified to incorporate the teachings of Xiong et al in order to allow for the power delivery module to incorporate a voltage regulator for greater control over the power delivered from the power deliver module. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW ZABEL whose telephone number is (703)756-4788. The examiner can normally be reached M-F 9-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff W Natalini can be reached at 572-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANDREW JOHN ZABEL/Examiner, Art Unit 2818 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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Prosecution Timeline

Jan 18, 2024
Application Filed
Mar 18, 2026
Non-Final Rejection mailed — §102, §103
Jun 18, 2026
Response Filed
Sep 01, 2026
Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+24.0%)
3y 4m (~8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 38 resolved cases by this examiner. Grant probability derived from career allowance rate.

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