DETAILED ACTION
This action is responsive to the election received on 06/08/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention/Group I (claims 1-11) in the reply filed on 08/06/2026 is acknowledged.
Claim(s) 12-13 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in REPUBLIC OF KOREA on 07/19/2021.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 01/18/2024 has/have been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 8 recite the limitation “an identification key generation portion that generates an identification key using at least one of a difference in electrical characteristics of the first semiconductor element portion due to a process deviation. . .” in lines 4-6 of the claims. This limitation is unclear for two reasons. The first reason is the use of the phrase “at least one of” which implies a list of options from which one of the options may be chosen. However, the claim recites only “a difference in electrical characteristics”. It is unclear if other options were intended to be considered and not included in the claim or if there is only one option of the difference in electrical characteristics which may be read on the claim. The second reason is the use of the phrase “difference in electrical characteristics . . . due to a process deviation occurring in the manufacturing process” which implies a difference relative to some other value which has not been provided in the claim. It is unclear if the difference may be relative to another semiconductor element portion or a difference relative to some reference value, neither of which have been recited in the claim. Therefore, claims 1 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 2-7 and 9-10 are rejected under 35 U.S.C. 112(b) at least for their dependencies. For the purposes of this examination, the limitation of claims 1 and 8 will be interpreted to read as “an identification key generation portion that generates an identification key using a difference in electrical characteristics of the first semiconductor element portion due to a process deviation. . .” and a difference relative to another device or an intended reference value will be interpreted to read on the claims.
Claim 5 recites the limitation “the identification key generation portion includes a first transistor and a second transistor designed to the same size using the second semiconductor element portion . . . the identification key using differences in electrical characteristics resulting from process deviations occurring in the manufacturing process of the first transistor and the second transistor” (i.e. identification key is due to differences in the second portion). However, claim 1, which claim 5 depends on, has previously recited “identification key generation portion that generates an identification key using a difference in electrical characteristics of the first semiconductor element portion due to a process deviation” (i.e. identification key is due to differences in the first portion). These statements appear to directly contradict one another such that it is unclear which semiconductor element portion’s manufacturing process differences are being used to generate the identification key. Therefore, claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 6-7 are rejected under 35 U.S.C. 112(b) at least for their dependencies. For the purposes of this examination, claim 5 will be interpreted to read as “the identification key generation portion includes a first transistor and a second transistor designed to the same size using the first semiconductor element portion . . . the identification key using differences in electrical characteristics resulting from process deviations occurring in the manufacturing process of the first transistor and the second transistor”.
Claim 7 recites the limitation “the channel layer of the first transistor has either a disordered polycrystalline film structure or a preferentially oriented polycrystalline thin film structure”. It is unclear what the term “preferentially” is modifying in this context and how it modifies the phrase. Under one interpretation, the use of the term “preferentially” here could be intended to say the oriented polycrystalline film is preferential to the disordered film. Under an alternative interpretation, the term “preferentially” could be used to describe an oriented film which is different in some manner from a non-preferentially ordered film. In the latter interpretation, it is not made clear by the claims or the specification what differences may be observed to differentiate a “preferentially” ordered film from one which is not “preferentially” ordered. Therefore, claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this examination, the limitation of claim 7 will be interpreted to read as “the channel layer of the first transistor has either a disordered polycrystalline film structure or an oriented polycrystalline thin film structure”.
Claim 11 recites the limitation “the first process is performed on a semiconductor substrate, the second process is performed above the first process” while claim 11 is a device claim. This is interpreted as a combination of a product and a process in the same claim (see MPEP 2173.05(p).II). It is unclear what implications this process description has on the structure of the device since a process being performed “above” another process could encompass a hierarchy (or order) of steps or could imply some relative structural positioning of the device during manufacture without detailing how the positioning during manufacture may influence the final device structure. Therefore, claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. For the purposes of this examination, the limitation of claim 11 will be interpreted to encompass any device where two separate processes are used in the manufacturing of the device where the second process may always be interpreted as being performed “above” the second process either by occurring before it (above in order) or by occurring after it (above in structure) since any direction may be the “above” direction.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 5, 8, and 9 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by US 2020/0366507 A1; Lu, Shih-Lien Linus; 11/2020; (“Lu”).
Regarding Claim 1. Lu discloses An identification key generation circuit using process deviation (#100, Figure 1, PUF circuitry which considers “manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process” according to [0013]) comprising:
a first semiconductor element portion (#102, Figure 1, difference generator circuit including transistors that comprise semiconductors according to [0014]) and a second semiconductor element portion (#106, Figure 1, sense amplifier including transistors that comprise semiconductors according to [0016]) manufactured on a single semiconductor substrate ([0001], “integrated circuit represents a collection of electronic circuits that are formed onto a semiconductor substrate”, i.e. these structures are on a semiconductor substrate) and have different physical characteristics ([0014] and [0016], the transistors of #102 and #106 include different physical characteristics including the #102 includes only p-type while #106 includes n-type transistors);
an identification key generation portion that generates an identification key using a difference in electrical characteristics of the first semiconductor element portion due to a process deviation occurring in the manufacturing process of the first semiconductor element portion ([0014], the transistors of #102 generate an analog difference in their electrical properties based on differences in their fabrication processes); and
an identification key derivation portion that determines the difference in electrical characteristic as a digital value ([0016], the transistors of #106 output a digital 1 or 0 depending on differences in the electrical outputs of the transistors of #102);
wherein the first semiconductor element portion is formed on the semiconductor substrate ([0001], “integrated circuit represents a collection of electronic circuits that are formed onto a semiconductor substrate”, i.e. these structures are on a semiconductor substrate, i.e. #102 is necessarily on a semiconductor substrate, where “on” does not require direct contact), and the second semiconductor element portion is formed on the upper portion of the first semiconductor element portion (Figure 1, #106 is necessarily formed “on” the upper portion of #102 where “on” does not require direct contact or relative positioning, the device may be rotates as necessary to have #106 on a top portion of #102), and
wherein the first semiconductor element portion and the second semiconductor element portion are connected to each other through at least one layer of via-holes, metal wiring, and contact hole layers (Figure 1, #102 and #106 are at least partially connected by the plurality of metal wiring lines).
Regarding Claim 2. Lu discloses The identification key generation circuit using process deviation according to claim 1, wherein the identification key derivation portion is formed from the first semiconductor element portion (Figure 1, the transistors Q7 and Q8 may be interpreted as having been made from the same semiconductor element portion as Q1 and Q2 since they are all p-type).
Regarding Claim 4. Lu discloses The identification key generation circuit using process deviation according to claim 1, wherein the first semiconductor element portion is produced through any one of a complementary metal oxide semiconductor manufacturing process, an amorphous silicon thin film transistor manufacturing process, and a polycrystalline silicon thin film transistor manufacturing process (Figure 1, [0014], #102 is formed using PMOS manufacturing as part of the larger CMOS manufacturing used to make the entire device which includes PMOS and NMOS devices).
Regarding Claim 5. Lu discloses The identification key generation circuit using process deviation according to claim 1,
wherein the identification key generation portion includes a first transistor and a second transistor designed to the same size using the first semiconductor element portion ([0014], the Q1 and Q2 of #102 are intended to be made as the same size in the fabrication process), and
wherein the identification key generation portion generates the identification key using differences in electrical characteristics resulting from process deviations occurring in the manufacturing process of the first transistor and the second transistor ([0014], differences in the electrical properties of Q1 and Q2 of #102 are a result of uncontrollable random physical processes during the manufacturing process which are subsequently used to form the PUF).
Regarding Claim 8. Lu discloses An identification key generation circuit using process deviation (#100, Figure 1, PUF circuitry which considers “manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process” according to [0013]) comprising:
a first semiconductor element portion (#106, Figure 1, sense amplifier including transistors that comprise semiconductors according to [0016]) and a second semiconductor element portion (#102, Figure 1, difference generator circuit including transistors that comprise semiconductors according to [0014]) manufactured on a single semiconductor substrate ([0001], “integrated circuit represents a collection of electronic circuits that are formed onto a semiconductor substrate”, i.e. these structures are on a semiconductor substrate) and have different physical characteristics ([0014] and [0016], the transistors of #102 and #106 include different physical characteristics including the #102 includes only p-type while #106 includes n-type transistors);
an identification key generation portion that generates an identification key using a difference in electrical characteristics of the second semiconductor element portion due to a process deviation occurring in the manufacturing process of the second semiconductor element portion ([0014], the transistors of #102 generate an analog difference in their electrical properties based on differences in their fabrication processes);
a storage portion that stores the difference in electrical characteristics (#110, Figure 1, storage circuit that stores the output of the difference in electrical characteristics according to [0019]); and
an identification key derivation portion that determines the difference in electrical characteristic as a digital value using the storage portion ([0016], the transistors of #106 output a digital 1 or 0 depending on differences in the electrical outputs of the transistors of #102);
wherein the first semiconductor element portion is formed on the semiconductor substrate ([0001], “integrated circuit represents a collection of electronic circuits that are formed onto a semiconductor substrate”, i.e. these structures are on a semiconductor substrate, i.e. #106 is necessarily on a semiconductor substrate, where “on” does not require direct contact), and the second semiconductor element portion is formed on the upper portion of the first semiconductor element portion (Figure 1, #102 is necessarily formed “on” the upper portion of #106 where “on” does not require direct contact or relative positioning, the device may be rotates as necessary to have #102 on a top portion of #106), and
wherein the first semiconductor element portion and the second semiconductor element portion are connected to each other through at least one layer of via-holes, metal wiring, and contact hole layers (Figure 1, #102 and #106 are at least partially connected by the plurality of metal wiring lines).
Regarding Claim 9. Lu discloses The identification key generation circuit using process deviation according to claim 8,
wherein the identification key generation portion includes a first transistor and a second transistor designed to the same size using the second semiconductor element portion ([0014], the Q1 and Q2 of #102 are intended to be made as the same size in the fabrication process), and
wherein the identification key generation portion generates the identification key using differences in electrical characteristics resulting from process deviations occurring in the manufacturing process of the first transistor and the second transistor ([0014], differences in the electrical properties of Q1 and Q2 of #102 are a result of uncontrollable random physical processes during the manufacturing process which are subsequently used to form the PUF).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 6, 10, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0366507 A1; Lu, Shih-Lien Linus; 11/2020; (“Lu”) as applied to claims 1, 5, and 9 above, and further in view of Recent progress in low-temperature-process monolithic three dimension technology; Yang et al.; 03/2018; (“Yang”).
Regarding Claim 3. Lu discloses The identification key generation circuit using process deviation according to claim 1.
Lu does not disclose that the second semiconductor element portion (#106, Figure 1, sense amplifier including transistors that comprise semiconductors according to [0016]) includes a transition metal oxide containing one or more positive ions among In, Zn, Ga, and Sn. The transistors of #106 in Figure 1 are described as being formed through NMOS and PMOS processing in [0016].
However, Yang teaches the monolithic formation of a physically unclonable function cell using a transistor and further teaches that the transistor may be IGZO based such that it includes a transition metal oxide of In, Zn, and Ga (see page 2, left column, third paragraph).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the transistors of Lu to have transition metal oxide channels in the PUF circuit as was considered by Yang since IGZO has a higher bandgap to facilitate low-leakage-current transistors (see page 2, left column, third paragraph).
Regarding Claim 6. Lu discloses The identification key generation circuit using process deviation according to claim 5.
Lu does not disclose that a channel layer of the first transistor ([0014], the Q1 of #102) includes a polycrystalline oxide thin film including at least one of IGZO, binary, three-component, four-component, and five-component system, and wherein the binary system includes at least one of ZnO, In2O3, Ga2O3, and SnO2, and wherein the three-component system includes at least one of InGaO, InZnO, GaZnO, and ZnSnO, wherein the four-component system includes at least one of InGaSnO and InZnSnO, and wherein the five-component system includes InGaZnSnO. The transistors of #102 in Figure 1 are described as being formed through NMOS and PMOS processing in [0014].
However, Yang teaches the monolithic formation of a physically unclonable function cell using a transistor and further teaches that the transistor may be IGZO based (see page 2, left column, third paragraph).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the transistors of Lu to have IGZO channels in the PUF circuit as was considered by Yang since IGZO has a higher bandgap to facilitate low-leakage-current transistors (see page 2, left column, third paragraph).
Regarding Claim 10. Lu discloses The identification key generation circuit using process deviation according to claim 9, wherein a manufacturing process of the first semiconductor element portion (#106, Figure 1, sense amplifier including transistors that comprise semiconductors according to [0016]) is a silicon semiconductor manufacturing process ([0016], the transistors of #106 are formed through metal-oxide-semiconductor manufacturing which may include silicon according to [0001]).
Lu does not disclose that the manufacturing process of the second semiconductor element portion (#102, Figure 1, difference generator circuit including transistors that comprise semiconductors according to [0014]) is an oxide semiconductor manufacturing process. The transistors of #102 in Figure 1 are described as being formed through PMOS processing in [0014].
However, Yang teaches the monolithic formation of a physically unclonable function cell using a transistor and further teaches that the transistor may be IGZO based (see page 2, left column, third paragraph).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the transistors of Lu from oxide semiconductor manufacturing processes in the PUF circuit as was considered by Yang since IGZO has a higher bandgap to facilitate low-leakage-current transistors (see page 2, left column, third paragraph).
Regarding Claim 11. Lu discloses An identification key generation circuit using process deviation (#100, Figure 1, PUF circuitry which considers “manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process” according to [0013]) comprising:
a first transistor (Q7, Figure 1) configured to connect a second output node (node A, Figure 1) and a first reference voltage (#Vcc through Q10, Figure 1) to each other according to a voltage of a first output node (node B, Figure 1) (Figure 1, node B controls the gate on Q7 to allow connection between Vcc and node A);
a second transistor (Q8, Figure 1) configured to connect the first output node (node B, Figure 1) and the first reference voltage (#Vcc through Q10, Figure 1) according to the voltage of the second output node (node A, Figure 1) (Figure 1, node A controls the gate on Q8 to allow connection between Vcc and node B);
a third transistor (Q5, Figure 1) configured to connect the second output node (node A, Figure 1) and a second reference voltage (ground through Q9, Figure 1) according to the voltage of the first output node (node B, Figure 1) (Figure 1, node B controls the gate on Q5 to allow connection between ground and node A); and
a fourth transistor (Q6, Figure 1) configured to connect the first output node (node B, Figure 1) and the second reference voltage (ground through Q9, Figure 1) according to the voltage of the second output node (node A, Figure 1) (Figure 1, node A controls the gate on Q6 to allow connection between ground and node B);
wherein the first transistor and the second transistor are formed through a second process (Figure 1, Q7 and Q8 are PMOS devices formed through PMOS processing),
wherein the third transistor and the fourth transistor are formed through a first process (Figure 1, Q5 and Q6 are NMOS devices formed through NMOS processing),
wherein the first process is one of a complementary metal oxide semiconductor manufacturing process, an amorphous silicon thin film transistor manufacturing process, and a polycrystalline silicon thin film transistor manufacturing process ([0016], NMOS processing is part of CMOS processing which combines NMOS and PMOS),
wherein the first process is performed on a semiconductor substrate ([0001], “integrated circuit represents a collection of electronic circuits that are formed onto a semiconductor substrate”, i.e. these structures are on a semiconductor substrate, i.e. NMOS transistors are necessarily on a semiconductor substrate, where “on” does not require direct contact), the second process is performed above the first process (Figure 1, PMOS transistors are necessarily formed “on” the upper portion of NMOS transistors where “on” does not require direct contact or relative positioning, the device may be rotates as necessary to have PMOS portions on top of NMOS portions), and
wherein the transistor formed by the first process and the transistor formed by the second process are connected to each other through at least one layer of via-holes, metal wiring, and contact holes (Figure 1, all of the transistors are at least partially connected by the plurality of metal wiring lines).
Lu does not disclose that the second process is one of an oxide thin film transistor manufacturing process and an organic thin film transistor manufacturing process. The Q7 and Q8 transistors of #106 in Figure 1 are described as being formed through PMOS processing in [0016].
However, Yang teaches the monolithic formation of a physically unclonable function cell using a transistor and further teaches that the transistor may be IGZO based (see page 2, left column, third paragraph).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the transistors of Lu from oxide semiconductor thin film transistor manufacturing processes in the PUF circuit as was considered by Yang since IGZO has a higher bandgap to facilitate low-leakage-current transistors (see page 2, left column, third paragraph).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0366507 A1; Lu, Shih-Lien Linus; 11/2020; (“Lu”) in view of Recent progress in low-temperature-process monolithic three dimension technology; Yang et al.; 03/2018; (“Yang”) as applied to claim 6 above, and further in view of The Mobility Enhancement of Indium Gallium Zinc Oxide Transistors via Low-temperature Crystallization using a Tantalum Catalytic Layer; Shin et al.; 09/2017; (“Shin”)
Regarding Claim 7. Lu in view of Yang disclose The identification key generation circuit using process deviation according to claim 6.
Lu in view of Yang do not disclose that the channel layer of the first transistor has either a disordered polycrystalline thin film structure or an oriented polycrystalline thin film structure.
However, Shin teaches a method for forming an IGZO transistor to have a polycrystalline channel structure (see Methods section of Shin).
Since Lu in view of Yang is silent regarding the crystallinity or lack thereof, of the IGZO channel in their transistor, this would motivate one of ordinary skill to seek out teachings such as Shin in order to practice the invention of Lu in view of Yang. It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to consider forming the channel of the IGZO transistor to be polycrystalline, either disordered or oriented, from the teachings of Shin since doing so dramatically increases the field-effect mobility of the transistor when compared to an amorphous IGZO transistor as taught by Shin in their abstract.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2020/0059234 A1; Wang et al.; 02/2020 – Figures 3-4 disclose a PUF structure comprising two transistors (#110/#120) which are made to be identical but have random uncontrollable variations resulting in differences in their electrical properties which are measured by an overlying integrator/comparator circuit to generate a random value (see [0047]-[0053]).
US 9,972,586 B2; Okagaki, Takeshi; 05/2018 – Figures 1-3 and 7 disclose a PUF structure (#30) comprising a plurality of transistors which are made to be identical but have random uncontrollable variations resulting in differences in their electrical properties which are measured by a response signal creating circuit (#31).
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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