Prosecution Insights
Last updated: October 23, 2026
Application No. 18/580,659

DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS

Non-Final OA §102§103
Filed
Jan 19, 2024
Priority
Jul 25, 2022 — nonprovisional of PCTCN2022107645
Examiner
GRAY, AARON J
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE Technology Group Co., Ltd.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
429 granted / 521 resolved
+14.3% vs TC avg
Strong +30% interview lift
Without
With
+29.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
36 currently pending
Career history
557
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
53.0%
+13.0% vs TC avg
§102
28.5%
-11.5% vs TC avg
§112
15.7%
-24.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 521 resolved cases

Office Action

§102 §103
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I in the reply filed on 07/27/2026 is acknowledged. Claims 17-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/27/2026. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: “DISPLAY PANEL HAVING SPACER PILLARS, MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS” . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 3-7, 14 and 19 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Yoshimoto et. Al. (US 20150378226 A1 hereinafter Yoshimoto). Regarding claims 1 and 19, Yoshimoto teaches in Figs. 6-8E with associated text a display apparatus [0080] comprising a display panel, comprising an array substrate BS1-BP and a color filter substrate BS2-OC opposite to each other, wherein the color filter substrate comprises a first substrate BS2 (Figs. 6-7, [0082]), a plurality of spacer pillars (MSP, SSP and portion of OC thereon) (Figs. 6-7, [0083]), and a plurality of color filter layers CF (Figs. 6-7, [0082]), the spacer pillars and the color filter layers are on a side of the first substrate facing the array substrate (Figs. 4 and 6-7, [0082]), and the first substrate comprises a plurality of pixel regions DA and a spacing region NDA between adjacent pixel regions; each spacer pillar is in the spacing region (Fig. 6, [0065]), and each pixel region is provided with the color filter layer (Fig. 6); each spacer pillar comprises at least one spacer layer each made of the same material as the color filter layer in one of the pixel regions ([0068]); the array substrate comprises a second substrate BS1 and a support layer (structures thereon including layers M1-BP), wherein the support layer is on a side of the second substrate facing the color filter substrate (Fig. 7, [0065]), and comprises a body layer and a plurality of protrusions BP on a side of the body layer away from the second substrate (Fig. 7), and at least one of the protrusions is each opposite to one of the spacer pillars; and at least one of the spacer pillars is each in direct contact with a corresponding protrusion (Fig. 7, [0067]). Regarding claim 3, Yoshimoto teaches the protrusions are made of a material comprising an organic material ([0055]). Regarding claim 4, Yoshimoto teaches the body layer and the protrusions form an integral structure (they are part of the same structure and are therefore interpreted to be an integral structure the claim wouldn’t necessarily require them to be made of a Fig. 7). Regarding claim 5, Yoshimoto teaches a ratio of a height of each spacer pillar to a height of the corresponding protrusion is 0.5 to 1.3 (BP has a height of 4 microns [0050] and SP has a height of 2 microns [0066] so that a ratio is 0.5). Regarding claims 6, Yoshimoto teaches the color filter substrate further comprises a black matrix BM in the spacing region; and each spacer pillar is on a side of the black matrix away from the first substrate (Fig. 6-7, [0057]), and an orthographic projection of the black matrix on the first substrate covers an orthographic projection of the spacer pillar on the first substrate (Fig. 6). Regarding claims 7, Yoshimoto teaches each spacer pillar is opposite to one of the protrusions (Fig. 7); the plurality of spacer pillars comprise at least one main spacer pillar MSP and a plurality of auxiliary spacer pillars SSP; each main spacer pillar is in direct contact with a protrusion opposite to the main spacer pillar; and each auxiliary spacer pillar is spaced apart from a protrusion opposite to the auxiliary spacer pillar (Figs. 6-7, [0084]). PNG media_image1.png 20 233 media_image1.png Greyscale Regarding claims 14, Yoshimoto teaches the array substrate further comprises a plurality of gate lines G and a plurality of data lines D on the second substrate (Fig. 8B [0091]-[0092]), the plurality of gate lines and the plurality of data lines are intersected with each other, and an orthographic projection of each gate line on the first substrate and an orthographic projection of each data line on the first substrate are both within the spacing region (Fig. 8B); and an orthographic projection of at least one of the spacer pillars on the first substrate is within the orthographic projection of the gate line on the first substrate (Figs. 6-7 and 8B). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimoto as applied to claim 1 and further in view of Lim et. Al. (US 20050190338 A1 hereinafter Lim). Regarding claim 2, Yoshimoto teaches the display panel according to claim 1. Yoshimoto does not specify the protrusions have a hardness lower than a hardness of the spacer layer. Lim discloses in Figs. 9 with associated text a device similar to that of Yoshimoto wherein protrusions (protruding portion od layers 106-107) have a hardness lower than a hardness of the spacer layer (301 or 302) (Fig. 9, [0084]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a structure with hardnesses similar to that of Lim on the device of Yoshimoto because according to Lim a reduction of frictional forces between the second column spacer 302 and the first substrate 100 may be obtained, thereby reducing the spots on the screen [0086]. Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimoto as applied to claim 7 and further in view of Yagi et. Al. (US 20050151909 A1 hereinafter Yagi). Regarding claim 8, Yoshimoto teaches the display panel according to claim 7, wherein the color filter substrate comprises color filter layers of N colors. Yoshimoto does not specify each spacer layer corresponds to a color filter layer of one color, and different spacer layers in the same spacer pillar correspond to color filter layers of different colors; each spacer layer is made of the same material and has the same thickness as the corresponding color filter layer; and the main spacer pillar comprises N spacer layers, and each auxiliary spacer pillar comprises M spacer layers, where M and N are both positive integers, and M<N. Yagi discloses in Figs. 1-3 with associated text a device similar to that of Yoshimoto wherein each spacer layer 23a, 23b and 23s corresponds to a color filter layer of one color, and different spacer layers in the same spacer pillar correspond to color filter layers of different colors (Fig. 1, [0043]); each spacer layer is made of the same material and has the same thickness as the corresponding color filter layer (Fig. 1, [0043]); and the main spacer pillar 29 comprises N spacer layers (3 spacer layers (Fig. 1, [0043])), and each auxiliary spacer pillar 28 comprises M spacer layers (2 layers (Fig. 1, [0044])), where M and N are both positive integers, and M<N (Fig. 1, [0043]-[0044]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a structure similar to that of Yagi for forming the spacer pillars of Yoshimoto because according to Yagi the main spacer functions as a part of a spacer for keeping the distance between the color filter substrate 20 and the TFT array substrate 10 to be consistent.[0046] and in the auxiliary spacer pillar layers are superposed onto each other, so that color layer superposition sections 28 are formed in order to prevent the leakage of light [0044]. Regarding claim 9, Yoshimoto in view of Yagi teaches the display panel according to claim 8. Yoshimoto does not specify orthographic projections of the N spacer layers in the main spacer pillar on the first substrate have the same area. Yagi discloses in another embodiment in Fig. 14 with associated text a device similar to that of Yoshimoto in view of Yagi wherein orthographic projections of the N spacer layers 83a-83c in a main spacer pillar on the first substrate have the same area (Fig. 14, [0044]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a structure similar to that of Yagi for forming the spacer layers of the main spacer pillars of Yoshimoto in view of Yagi because according to Yagi the structure provides a liquid crystal display apparatus that prevents the short circuit between the opposing electrode 85 and the pixel electrodes 74 by removing either (i) an area of the opposing electrode 85 formed on said at least one protruding structure section 84 on the color filter substrate 80 shown in FIG. 14, the area facing the pixel electrodes 74 (hereinafter, this area will be referred to as a facing area of the opposing electrode 85) or (ii) an area of the pixel electrodes 74, the area facing the opposing electrode 85 formed on said at least one protruding structure section 84 [0007]. Regarding claim 10, Yoshimoto teaches the display panel according to claim 6. Yoshimoto does not specify each spacer pillar comprises a plurality of spacer layers, and orthographic projections of the plurality of spacer layers in each of at least one of the spacer pillars on the first substrate are sequentially reduced in area in a direction away from the black matrix. Yagi discloses in Figs. 1-3 with associated text a device similar to that of Yoshimoto wherein each spacer pillar (24 and 25 and 36 thereon) comprises a plurality of spacer layers (at least 23a and 23b) (Fig. 1, [0045]), and orthographic projections of the plurality of spacer layers in each of at least one of the spacer pillars on the first substrate are sequentially reduced in area in a direction away from the black matrix 22 (Figs. 1 and 3, [0045]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a structure similar to that of Yagi for forming the spacer pillars of Yoshimoto because according to Yagi the main spacer functions as a part of a spacer for keeping the distance between the color filter substrate 20 and the TFT array substrate 10 to be consistent.[0046]. Regarding claim 11, Yoshimoto in view of Yagi teaches the display panel according to claim 10. Yoshimoto does not specify a ratio of a width of a spacer layer closest to the black matrix in each spacer pillar to a width of the black matrix is between 0.5 and 1; and a ratio of an area of a spacer layer farthest from the black matrix in the spacer pillar to an area of the spacer layer closest to the black matrix is between 1/6 and ½, however Yagi depicts a ratio of a width of a spacer layer closest to the black matrix in each spacer pillar to a width of the black matrix is between 0.5 and 1 (Fig. 3); and a ratio of an area of a spacer layer farthest from the black matrix Blue in the spacer pillar to an area of the spacer layer closest to the black matrix R is between 1/6 and ½ (Fig. 3) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to follow the guidance in the drawing of Yagi in Fig. 3 to make a ratio of a width of a spacer layer closest to the black matrix in each spacer pillar to a width of the black matrix is between 0.5 and 1; and a ratio of an area of a spacer layer farthest from the black matrix in the spacer pillar to an area of the spacer layer closest to the black matrix is between 1/6 and ½, furthermore Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to make a ratio of a width of a spacer layer closest to the black matrix in each spacer pillar to a width of the black matrix is between 0.5 and 1; and a ratio of an area of a spacer layer farthest from the black matrix in the spacer pillar to an area of the spacer layer closest to the black matrix is between 1/6 and ½ with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). Regarding claim 12, Yoshimoto teaches the display panel according to claim 1. Yoshimoto does not specify at least two adjacent color filter layers of the same color are connected into an integral structure. Yagi discloses in Figs. 1-3 with associated text a device similar to that of Yoshimoto wherein at least two adjacent color filter layers of the same color are connected into an integral structure (Fig. 1, [0044]-[0045]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a structure similar to that of Yagi for forming the color filters of Yoshimoto because according to Yagi the main spacer functions as a part of a spacer for keeping the distance between the color filter substrate 20 and the TFT array substrate 10 to be consistent.[0046] and in the auxiliary spacer pillar layers are superposed onto each other, so that color layer superposition sections 28 are formed in order to prevent the leakage of light [0044]. Regarding claim 13, Yoshimoto in view of Yagi teaches at least one of the spacer layers (23c of Yagi for example) and an adjacent color filter layer are connected into an integral structure (Fig. 1, [0045] of Yagi). Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimoto as applied to claim 1 and further in view of Chae et. Al. (US 20080259255 A1 hereinafter Chae). Regarding claim 15, Yoshimoto teaches the display panel according to claim 1, wherein the array substrate further comprises a thin film transistor TR (Fig. 7, [0076]), and a pixel electrode EL2 (Fig. 2, [0076]); the thin film transistor is between the second substrate and the support layer (here the support layer is taken to be PSV and BP only) (Fig. 7); and the pixel electrode is on a side of the support layer away from the second substrate (Fig. 7), and connected to a drain of the thin film transistor through a via in the body layer. Yoshimoto does not specify the pixel electrode is connected to a drain of the thin film transistor through a via in the body layer. Chae discloses in Fig. 3 with associated text a device similar to that of Yoshimoto wherein a pixel electrode 118 is connected to a drain 117 of a thin film transistor (112-117) through a via in a body layer 126 (Fig. 3, [0048]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a structure similar to that of Chae for forming the drain electrode and pixel electrode of Yoshimoto because according to Chae the TFT supplies a pixel signal through a data line to a pixel electrode 118, in response to a scanning signal through the gate line. The pixel electrode 118 is in contact with the drain electrode 117 through a contact hole in a protective film 126. A common electrode 113 is formed in the form of a stripe such that it is alternatively arranged with the pixel electrode 118. The common electrode 113 applies a common voltage which is a base voltage of liquid crystal driving. [0048] so that such a structure would be suitable for driving the pixel of Yoshimoto. Regarding claim 16, Yoshimoto teaches the orthographic projection of the spacer pillar on the first substrate is not overlapped with an orthographic projection of the thin film transistor on the first substrate (Fig. 7). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toledo Fernando can be reached on 5712721867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AARON J GRAY/Examiner, Art Unit 2897
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Prosecution Timeline

Jan 19, 2024
Application Filed
Sep 28, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+29.8%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 521 resolved cases by this examiner. Grant probability derived from career allowance rate.

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