DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 6/25/2026. Claims 1-2 and 4-17 are pending in this application. Claims 1, 4-5, 9, 13, and 15 are amended. Claim 3 is canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hatta et al. (JP 2015-95578; hereinafter ‘Hatta’).
Regarding claim 1, Hatta teaches a silicon carbide semiconductor device (Figures 1-3, [0014, 0020]) comprising:
a silicon carbide substrate (1a, which is silicon carbide, Figure 3, [0021]) having a first main surface (a surface on which the device elements are formed; hereinafter ‘1aFS’);
a gate pad (45, Figure 1, [0015]) and a source pad (41), the gate pad and the source pad being provided above the first main surface (45 and 41 are formed above 1aFS, since they are disposed on an interlayer insulating film 32 covering the semiconductor surface, Figures 1 and 3, [0033]),
wherein, in a plan view from a direction perpendicular to the first main surface (Figure 2, [0014]) the silicon carbide substrate (1a) includes
a first region (7, [0016]) that includes a plurality of unit cells (10),
a second region (a portion of the termination region overlapping 45 in plan view, Figures 1-3; hereinafter ‘R2’) that overlaps the gate pad (45), and
a third region (another portion of the termination region outside 7, Figures 1-3; hereinafter ‘R3’) that is continuous with the second region (R3 is continuous with R2),
where each of the unit cells (10) includes
a drift region (2, Figure 3, [0021]) that is of a first conductivity type (n-type),
a body region (20, Figure 3, [0023]) that is of a second conductivity type different from the first conductivity type (p-type),
a source region (12, Figure 3, [0024]) that is provided along the first main surface (12 is provided along 1aFS), is spaced apart from the drift region by the body region (12 is spaced apart from 2 by 20), and is of the first conductivity type (n-type),
a contact region (25, Figure 3, [0028]) that is provided along the first main surface (25 is provided along 1aFS), is electrically connected to the body region (25 is electrically connected to 20), and is of the second conductivity type (p-type),
a gate electrode (35, Figure 3, [0029]) electrically connected to the gate pad (35 electrically connected to 45 through 44, Figures 1 and 3, [0032]), and
a gate insulating film (30, Figure 3, [0029]) provided between the gate electrode and the drift region, the body region, and the source region (30 provided between 35 and 2/20/12),
where the second region (2R) has a first semiconductor region (a portion corresponding to 28, Figures 1-3, [0018]; hereinafter ‘1SR’), that is of the second conductivity type (p-type, [0030]),
the third region (3R) has a second semiconductor region (a portion corresponding to 21, Figures 2 and 3; hereinafter ‘2SR’) that is of the second conductivity type (p-type, [0030]),
the first semiconductor region and the second semiconductor region are continuous with each other along the first main surface (1SR and 2SR are continuous with each other along 1aFS, Figure 3), and
an interlayer insulating film (32, Figure 3, [0073]) provided between the first semiconductor region and the gate pad (32 provided between 28 and 45, since 45 is disposed on 32, Figures 1 and 3, [0033]),
wherein the source region, the contact region, and the second semiconductor region are electrically connected to the source pad (12, 25, and 21 are electrically connected to 41), and
wherein, in the plan view, the unit cells extend in a first direction and are arranged at a first pitch in a second direction that is perpendicular to the first direction (unit cells 10 extend in a first direction (left to right) and are arranged at a first pitch in a perpendicular direction (top to bottom), Figures 2 and 6, [0016, 0041]).
Hatta does not specify that a dimension of the second semiconductor region in a direction away from the second region is greater than or equal to the first pitch.
Hatta, however, discloses that unit cells 10 are arranged at a repeating pitch within active region 7 and that the portion of termination well region 21 corresponding to the second semiconductor region in R3 extends away from the gate pad overlapping second region R2 along the outside of active region 7 (FIGS. 2, 3, and 6, [0016, 0018, 0020, 0030, 0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Hatta to obtain the silicon carbide semiconductor device, wherein a dimension of the second semiconductor region in a direction away from the second region is greater than or equal to the first pitch as claimed, because selecting a lateral dimension of at least one unit-cell pitch would have been a predictable design choice for providing sufficient space to accommodate termination well region 21 and termination low-resistance region 28 adjacent to the repeated unit-cell array. This configuration maintains the reduced parasitic resistance and improved dV/dt withstand capability provided by termination low resistance region 28 [0018, 0030, 0053].
Regarding claim 9, Hatta teaches the silicon carbide semiconductor device according to claim 1, wherein the interlayer insulating film (32, Figure 3, [0073]) is formed in the first region and the third region (32 is formed in 7 and 3R),
for each of the unit cells, a first contact hole (a contact hole formed in 32 and filled with 40 within 7, Figure 3, [0025]; hereinafter ‘CH1’) is formed in the interlayer insulating film within the first region (CH1 is formed in 32 within 7), the first contact hole reaching the source region and the contact region (CH1 reaching 12 and 25, [0074]),
a second contact hole (a contact hole formed in 32 and filled with 40 within the termination region outside 7, Figure 3; hereinafter ‘CH2’) is formed in the interlayer insulating film within the third region (CH1 is formed in 32 within R3), the second contact hole reaching the second semiconductor region (CH2 reaching 2SR. [0074]).
Hatta does not explicitly teach that the first contact hole and the second contact hole are arranged at a predetermined pitch in the second direction.
Hatta, however, disclosed that the contact holes are patterned using photogravure, such that the positions of the contact holes correspond to a defined layout pattern of the patterned electrode [0076].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Hatta to obtain and achieve the silicon carbide semiconductor device wherein the first contact hole and the second contact hole are arranged at a predetermined pitch in the second direction as claimed, because the photogravure pattern forms structure according to a designed layout having defined positional relationships, which should have been understood as a predetermined pitch.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hatta (JP 2015-95578) in view of Arthur et al. (US 2013/0126971; hereinafter ‘Arthur’).
Regarding claim 2, Hatta teaches the silicon carbide semiconductor device according to claim 1, but does not teach the silicon carbide semiconductor device wherein the contact region and the second semiconductor region are continuous with each other along the first main surface.
Arthur teaches the silicon carbide semiconductor device (FIG. 9, [0066]) wherein the contact region (P+ body region 252) and the second semiconductor region (P-well region 228) are continuous with each other along the first main surface (252 and 228 are in contact and form a continuous P-type semiconductor region).
As taught by Arthur, one of ordinary skill in the art would utilize and modify the above teaching into Hatta to obtain and achieve the silicon carbide semiconductor device wherein the contact region and the second semiconductor region are continuous with each other along the first main surface as claimed, because contact resistance in P-type SiC regions is high, and forming a continuous contact structure reduce contact resistance and improves electrical connection [0070-0071].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Arthur in combination with Hatta due to the above reason.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Hatta (JP 2015-95578) in view of Zhang et al. (US 2019/0081624; hereinafter ‘Zhang’) and Kobayashi et al. (JP 2019-160901; hereinafter ‘Kobayashi’).
Regarding claim 4, Hatta teaches the silicon carbide semiconductor device according to claim 1, but does not teach the silicon carbide semiconductor device wherein the dimension of the second semiconductor region in the direction away from the second region is twice or more the first pitch.
Zhang teaches a silicon carbide semiconductor device (300, FIG. 5, [0084]) wherein the dimension of the second semiconductor region in the direction away from the second region (the portion of p-well 344 underlying an inactive region that extends 100-300 µm, [0085]).
As taught by Zhang, one of ordinary skill in the art would utilize and modify the above teaching into Hatta to obtain and achieve the silicon carbide semiconductor device wherein the dimension of the second semiconductor region in the direction away from the second region as claimed, because providing a relatively large area to accommodate the gate structure and associated bonding requirements inherently facilitates displacement current flow and current spreading during device operation [0050-0052].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Zhang in combination with Hatta due to the above reason.
Hatta in view of Zhang does not teach the silicon carbide semiconductor device wherein the dimension of the second semiconductor region in the direction away from the second region is twice or more the first pitch.
Kobayashi teaches a silicon carbide semiconductor device (MOSFET, [0031]) wherein a unit cell pitch is about 5 µm [0033].
As taught by Kobayashi, one of ordinary skill in the art would utilize and modify the above teaching into Hatta in view of Zhang to obtain and achieve the silicon carbide semiconductor device wherein the dimension of the second semiconductor region in the direction away from the second region is twice or more the first pitch as claimed, because reducing the unit cell pitch is a known technique to reduce on-resistance in trench MOSFET structure [0003], and such a reduced pitch inherently results in the dimension of the second semiconductor region being significantly greater than the pitch, thereby satisfying the claimed relationship (e.g., 100-300 µm versus about 5 µm).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Kobayashi in combination with Hatta in view of Zhang due to the above reason.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Hatta (JP 2015-95578) in view of Nakao et al. (US 2014/0299888; hereinafter ‘Nakao’).
Regarding claim 5, Hatta teaches the silicon carbide semiconductor device according to claim 1, wherein the third region (3R, Figure 3) includes a fourth region (a portion of the termination region disposed between 7 and 28, Figures 1 and 2; hereinafter ‘4R’) located between the first region (7) and the second region (2R) in the plan view (see the annotated Figure 2).
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Hatta does not teach that a dimension, in the second direction, of the second semiconductor region within the fourth region is greater than or equal to the first pitch.
Nakao teaches a silicon carbide semiconductor device (FIGS. 1 and 2, [0059]) including a fourth region (a region located between a MOSFET cell region and 11, FIG. 2, [0060]) and a second semiconductor region within the fourth region (14 provided on 1OM located below 11).
Nakao does not explicitly teach that a dimension, in the second direction, of the second semiconductor region is greater than or equal to the first pitch.
Nakao, however, teaches that the second semiconductor region 14 is laterally extended between the gate pad 11 and the MOSFET cell region and has a significantly larger transverse extend than the unit cell region [0008, 0126].
As taught by Nakao, one of ordinary skill in the art would utilize and modify the above teaching into Hatta to obtain and achieve the silicon carbide semiconductor device wherein the dimension, in the second direction, of the second semiconductor region within the fourth region is greater than or equal to the first pitch as claimed, because reducing resistance and suppressing potential drop in the semiconductor region below the gate pad are necessary to prevent electric field concentration and improve reliability during switching operation [0008-0012].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Nakao in combination with Hatta due to the above reason.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Hatta (JP 2015-95578) in view of Ohoka et al. (US 2019/0245052; hereinafter ‘Ohoka’).
Regarding claim 10, Hatta teaches the silicon carbide semiconductor device according to claim 1, wherein, in the plan view, the silicon carbide substrate has a rectangular shape (1a has a rectangular shape, since the outer shaper of the chip 5 corresponds to the outer shape of 1a, Figures 1-3, [0015]) having a first side, a second side, a third side, and a fourth side (1a having top, bottom, left, and right side edges), the first side and the second side being parallel to each other (top and bottom sides being parallel), and the third side and the fourth side being perpendicular to the first side and the second side (left and right sides being perpendicular to the top and bottom sides).
Hatta does not teach the silicon carbide semiconductor device wherein the silicon carbide semiconductor device further includes a first gate runner extending along the first side, a second gate runner extending along the second side, and a third gate runner continuous with the first gate runner and the second gate runner and extending along the third side, the gate pad is continuous with the first gate runner, and the second gate runner is spaced apart from the gate pad in a direction parallel to the third side.
Ohoka teaches a silicon carbide semiconductor device (201, FIG. 1A, [0029]) further includes
a first gate runner (a portion of 150 extending from 151 and disposed along a lower side of 101, [0031]; hereinafter ‘150B’) extending along the first side (a lower side of 101 extending in a direction parallel to 162A, [0032]; hereinafter ‘101B’),
a second gate runner (a horizontal portion of 152C, [0031]; hereinafter ‘152CH’) extending along the second side (an upper side of 101 extending in a direction parallel to 162C; hereinafter ‘101U’), and
a third gate runner (a vertical portion of 152C; hereinafter ‘152CV’) continuous with the first gate runner and the second gate runner (152CV continuous with 150B and 152CH) and extending along the third side (a right side of 101 extending in a direction parallel to 162D; hereinafter ‘101R’),
the gate pad is continuous with the first gate runner (151 is continuous with 150B), and
the second gate runner is spaced apart from the gate pad in a direction parallel to the third side (152CH is spaced apart from 151 in a direction parallel to 101R).
As taught by Ohoka, one of ordinary skill in the art would utilize and modify the above teaching into Hatta to obtain and achieve the silicon carbide semiconductor device wherein the silicon carbide semiconductor device further includes a first gate runner extending along the first side, a second gate runner extending along the second side, and a third gate runner continuous with the first gate runner and the second gate runner and extending along the third side, the gate pad is continuous with the first gate runner, and the second gate runner is spaced apart from the gate pad in a direction parallel to the third side as claimed, because providing gate runners as a continuous conductive structure connected to the gate pad facilitates transmission of gate signals to the gate electrode [0010] and reduces resistance and potential differences in the device [0061-0062], thereby improving operational stability.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Ohoka in combination with Hatta due to the above reason.
Regarding claim 11, Hatta in view of Ohoka teaches the silicon carbide semiconductor device according to claim 10, Hatta does not teach wherein the gate pad includes an intersection between the first gate runner and the third gate runner, and is continuous with the first gate runner and the third gate runner.
Ohoka teaches the silicon carbide semiconductor device wherein the gate pad includes an intersection between the first gate runner and the third gate runner (151 includes an intersection between 150B and 152CV, FIG. 1), and is continuous with the first gate runner and the third gate runner (151 is continuous with 150B and 152CV).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Ohoka to obtain and achieve the silicon carbide semiconductor device wherein the gate pad includes an intersection between the first gate runner and the third gate runner, and is continuous with the first gate runner and the third gate runner as claimed, because providing gate runners as a continuous conductive structure connected to the gate pad facilitates transmission of gate signals to the gate electrode [0010] and reduces resistance and potential differences in the device [0061-0062], thereby improving operational stability.
Regarding claim 12, Hatta in view of Ohoka teaches the silicon carbide semiconductor device according to claim 10, Hatta does not teach wherein the third gate runner is spaced apart from the gate pad in a direction parallel to the first side.
Ohoka teaches the silicon carbide semiconductor device wherein the third gate runner is spaced apart from the gate pad in a direction parallel to the first side (152CV is spaced apart from 115, with 112G disposed therebetween, FIG. 3A, [0065]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ and modify the teachings of Ohoka to obtain and achieve the silicon carbide semiconductor device wherein the third gate runner is spaced apart from the gate pad in a direction parallel to the first side as claimed, because overlapping of gate structure leads to increases potential difference and possible dielectric breakdown, and providing a spacing between the gate runner and the gate pad mitigates such effects [0065].
Claims 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Hatta (JP 2015-95578) in view of Ohoka (US 2019/0245052), further in view of Araoka (US 2020/0328301).
Regarding claim 14, Hatta in view of Ohoka teaches the silicon carbide semiconductor device according to claim 10, but does not teach wherein the third region includes an eighth region located along a side, closest to the second side, of the gate pad in the plan view, and the eighth region is spaced apart from the second gate runner.
Araoka teaches a silicon carbide semiconductor device (10, FIGS. 1 and 3, [0057-0058]) wherein the third region (a portion of 2 including 62a’, [0057, 0082]; hereinafter ‘3Raraoka’) includes an eighth region (a portion of 3Raraoka located adjacent to 12 along a side corresponding to a direction parallel to 14a’, [0059, 0065]; hereinafter ‘8R’) located along a side, closest to the second side, of the gate pad in the plan view (shown in FIG. 1), and the eighth region is spaced apart from the second gate runner (62a’, including 8R, is separated from 14a by an insulating layer 22, FIG. 3, [0073]).
As taught by Araoka, one of ordinary skill in the art would utilize and modify the above teaching into Hatta in view of Ohoka to obtain and achieve the silicon carbide semiconductor device wherein the third region includes an eighth region located along a side, closest to the second side, of the gate pad in the plan view, and the eighth region is spaced apart from the second gate runner as claimed, because direct proximity between a conductive gate runner and a semiconductor region can lead to electric filed concentration and dielectric breakdown, and separating the gate runner from the semiconductor region by an insulating layer mitigates such effects and improves device reliability [0053-0055].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Araoka in combination with Hatta in view of Ohoka due to the above reason.
Regarding claim 16, Hatta in view of Ohoka teaches the silicon carbide semiconductor device according to claim 10, but does not teach wherein the third region includes a ninth region located along a side, closest to the fourth side, of the gate pad in the plan view.
Araoka teaches the silicon carbide semiconductor wherein the third region (a portion of 2 including 62a’, FIGS. 1 and 3, [0057, 0082]; hereinafter ‘3Raraoka’) includes a ninth region (a portion of 3Raraoka located adjacent to 12 along the left side of 10 in FIG. 1, [0059, 0065]; hereinafter ‘8Rleft’) located along a side, closest to the fourth side, of the gate pad in the plan view (shown in FIG. 1).
As taught by Araoka, one of ordinary skill in the art would utilize and modify the above teaching into Hatta in view of Ohoka to obtain and achieve the silicon carbide semiconductor device wherein the third region includes a ninth region located along a side, closest to the fourth side, of the gate pad in the plan view as claimed, because semiconductor regions are provided to distribute electric fields and improve device reliability, and arranging such a region along a particular side of the gate pad is a predictable design choice [0061-0062].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Araoka in combination with Hatta in view of Ohoka due to the above reason.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Hatta (JP 2015-95578) in view of Ohoka et al. (US 2019/0244879; hereinafter ‘Ohoka79’).
Regarding claim 17, Hatta teaches the silicon carbide semiconductor device according to claim 1,
wherein the silicon carbide substrate has a rectangular shape (1a has a rectangular shape, since the outer shaper of the chip 5 corresponds to the outer shape of 1a, Figures 1-3, [0015]) having a first side, a second side, a third side, and a fourth side in the plan view (1a having top, bottom, left, and right side edges), the first side and the second side being parallel to each other (top and bottom sides being parallel), and the third side and the fourth side being perpendicular to the first side and the second side (left and right sides being perpendicular to the top and bottom sides),
the third region surrounds the gate pad in the plan view (3R surroun3R corresponding to 21 is disposed around the region including 45, thereby surrounding 45 in the plan view, Figures 1-3).
Hatta does not teach the silicon carbide semiconductor device further includes a first gate runner extending along the first side, a second gate runner extending along the second side, and a third gate runner continuous with the first gate runner and the second gate runner and extending along the third side, and a fourth gate runner connecting the third gate runner and the gate pad.
Ohoka79 teaches a silicon carbide semiconductor device (203, FIG. 7, [0105]) further includes
a first gate runner (a portion of the gate global wiring line g1 extending along S3, [0045, 0051]; hereinafter ‘g1S3’) extending along the first side (S3),
a second gate runner (a portion of the gate global wiring line g2 extending along S2; hereinafter ‘g2S2’) extending along the second side (S2), and
a third gate runner (a portion of g2 extending along S4; hereinafter ‘g2S4’) continuous with the first gate runner and the second gate runner (g2S4 continuous with g1S3 and g2S2) and extending along the third side (S4), and
a fourth gate runner (a portion of g1 extending along S1; hereinafter ‘g1S1’) connecting the third gate runner and the gate pad (g1S1 connecting g2S4 and GP, [0046]).
As taught by Ohoka79, one of ordinary skill in the art would utilize and modify the above teaching into Hatta to obtain and achieve the silicon carbide semiconductor device further includes a first gate runner extending along the first side, a second gate runner extending along the second side, and a third gate runner continuous with the first gate runner and the second gate runner and extending along the third side, and a fourth gate runner connecting the third gate runner and the gate pad as claimed, because providing a plurality of gate runners extending along respective sides of the substrate and forming a continuous connection therebetween allows each region to be surrounded by the gate wiring, thereby reducing variation in gate resistance and improving uniformity of operation [0104].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to employ the teaching as taught by Ohoka79 in combination with Hatta due to the above reason.
Allowable Subject Matter
Claims 6-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13 and 15 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The applied prior art neither anticipates nor renders the claimed subject matter obvious because it fails to teach the claimed a silicon carbide semiconductor device,
“wherein the dimension, in the second direction, of the second semiconductor region within the fourth region is twice or more the first pitch” as in the context of claim 6,
“wherein, in the plan view, the third region includes a fifth region located on one side, in the first direction, of the second region and of the fourth region, and
an area of the second semiconductor region within the fifth region is larger than or equal to an area of the second semiconductor region within the fourth region” as in the context of claim 7,
“wherein, in the plan view, the third region includes a sixth region located on an opposite side, in the first direction, of the second region and of the fourth region, and
an area of the second semiconductor region within the sixth region is larger than or equal to an area of the second semiconductor region within the fourth region” as in the context of claim 8,
“wherein the third region includes a seventh region located along a side, closest to the third side, of the gate pad in the plan view, and
the seventh region is continuous with the third gate runner” as in the context of claim 13, and
“wherein the third region includes an eighth region located along a side, closest to the second side, of the gate pad in the plan view, and the eighth region is continuous with the second gate runner” as in the context of claim 15.
The prior art of record includes Hatta, Nakao, Zhang, Kobayashi, and Ohoka. Hatta teaches a silicon carbide semiconductor device including an active region and a termination region configured to reduce resistance using semiconductor regions. Nakao teaches that a portion of the termination region has a significantly larger transverse extent than the unit cell region in the active region. Zhang teaches that the semiconductor region in the termination region extends on the order of 100-300 µm. Kobayashi teaches that a unit cell pitch is approximately 5 µm. Ohoka teaches a silicon carbide semiconductor device including a gate pad connected to a plurality of gate runners.
However, these prior art references, whether considered individually or in combination and/or with other prior arts references of record, do not meet all the limitations cited in claims 6-8, 13, and 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed on 6/25/2026 have been fully considered but they are not persuasive.
Applicant submits, in page 2 of Remark, that
“Hatta does not explicitly teach that a dimension of the second semiconductor region in a direction away from the second region is greater than or equal to the first pitch.
Accordingly, the feature of claim 1, namely “a dimension of the second semiconductor region in a direction away from the second region is greater than or equal to the first pitch” is a distinction over Hatta”.
The examiner respectfully disagrees.
As explained above, Hatta’s disclosed arrangement establishes the claimed dimensional relationship because the identified portion of termination well region 21 extends alongside a plurality of rows of unit cells 10 and encompasses at least one first pitch interval. Accordingly, Applicant’s asserted distinction does not overcome the rejection.
Applicant submits, in page 2 of Remark, that
“Here, MPEP 2125 II notes that proportions of features in a drawing are not evidence of actual proportions when drawings are not to scale. The Applicant respectfully submits that it would be improper to conclude that the termination region is depicted as extending over a distance that appears greater than the spacing between adjacent unit cells 10 because Hatta does not disclose that the drawings are drawn to scale”.
The examiner respectfully disagrees.
The rejection did not rely on measuring Figure 2 or treating its illustrated proportions as precise dimensions. Rather, Figure 2 is relied upon for the structural arrangement of termination well region 21 relative to the plurality of rows of unit cells 10, while Figure 6 further confirms the repeating arrangement of the unit cells. Accordingly, Applicant’s argument concerning the scale of Figure 2 does not overcome the rejection.
Applicant submits, in page 3 of Remark, that
“paragraphs [0004-0005] of Hatta merely relate to overcurrent detection and short-circuit tolerance at the time of a load short-circuit. Accordingly, the noted feature is not obvious to one of ordinary skill in the art before the effective filing date of the claimed invention”.
The examiner respectfully disagrees.
Paragraphs [0004]-[0005] are not the sole basis for the rejection. As explained above, the claimed dimensional relationship is supported by Hatta’s disclosed unit cell and termination region arrangement shown in Figures 1, 2, and 6 and described in paragraphs [0015-0018, 0030, 0041]. Accordingly, Applicant’s argument concerning paragraphs [0004]-[0005] does not overcome the rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 9/2/26
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