DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Amendment
Acknowledgment is made of applicant's Amendment, filed 02-05-2026. The changes and remarks disclosed therein have been considered.
Claim(s) 5 has/have been amended, claim(s) 11 has/have been cancelled, and claim(s) 1-10, 14-16, 18-21, 23, and 24 remain(s) pending in the application.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The first sentence of the abstract should be omitted.
Claim Objections
Claim(s) 5 is/are objected to because of the following informalities:
Claim(s) 5 recite(s) the language (emphasis added) “wherein rp=0.5,”, where “rp” is not the same variable as “rp”, and the variables should be formatted correctly.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-10, 14-16, 18-21, 23, and 24 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 1, 19, and 20 recite(s) the language (emphasis added) “based on model parameters of a target algorithm model, obtaining” and “obtaining an input set of the algorithm model, and”, where “target algorithm model” is not the same limitation as “algorithm model” and “the algorithm model” lacks antecedent basis and requires further clarification.
Claim(s) 1 and 20 recite(s) the language (emphasis added) “an influence factor that determines a critical weight device, determining” and “determining a critical weight device among the plurality of memristor devices according”, where “a critical weight device” is disclosed twice and it is unclear if the limitations are different from one another.
Claim(s) 2 recite(s) the language (emphasis added) “determining a way to obtain a first weight criticality of the plurality of memristor devices from the influence factor” and “determining a way to obtain a first weight criticality for each of the plurality of memristor devices from the first sub-influence factor”, where “a way” is already disclosed in claim 1, and it is unclear if the two recitations of “a way” in claim 2 are different from each other, and different from the recitation in claim 1.
Claim(s) 2 recite(s) the language (emphasis added) “each of the plurality of memristor devices from the first sub-influence factor”, where “the first sub-influence factor” lacks antecedent basis. The limitation “at least one first sub-influence factor” does no claim a particular “first sub-influence factor”.
Claims 5 introduces formula-based limitations (criticality computations) reciting variables {fli, xᵢ, g, rp, α, β} and unspecified summation bounds without clearly identifying:
• the summation domain (“over which set of inputs,” “across which devices,” etc.)
• the normalization or scaling basis
• whether rp is measured, predicted, or assigned
The claims do not provide operational boundaries for these variables nor a clear computational scope. The equations appear functional in nature and read like algorithmic expressions absent structural or definite algorithmic steps, resulting in unclear metes and bounds.
A skilled artisan cannot reasonably ascertain whether two implementations that produce different internal criticality values but same “critical device set” would infringe, nor whether differing hyperparameter choices fall within scope.
Thus, the claims lack clarity required by MPEP §2173.02.
Claim(s) 5 recite(s) the language (emphasis added) “determining a way to obtain a first weight criticality of the plurality of memristor devices from the influence factor”, where “a way” is already recited in claims 1 and 2 and it is unclear if the limitations are different.
Claim(s) 5 recite(s) the language (emphasis added) “in the first computing memristor array for the input value xi, where” and “xi is an input value for the memristor device R”, where “the input value” lacks antecedent basis, and it is unclear if “an input value” is the same limitation as the previously recited input value.
Claim(s) 5 recite(s) the language (emphasis added) “where fli is the first weight criticality value of the memristor device R for”, where “the memristor device R” lacks antecedent basis.
Claim(s) 5 recite(s) the language (emphasis added) “xi is an input value for the memristor device R in the i-th operation”, where “the i-th operation” lacks antecedent basis.
Claim(s) 5 recite(s) the language (emphasis added) “r(g) is a reliability risk coefficient in the case where”, where “the case” lacks antecedent basis.
Claim(s) 5 recite(s) the language (emphasis added) “α is a hyperparameter corresponding to the importance factor, β is a hyperparameter corresponding to the risk factor”, where “a hyperparameter” is recited twice and it is unclear if the limitations are the same.
Claim(s) 6 recite(s) the language (emphasis added) “determining a way to obtain a first weight criticality for”, where “a way” is already recited in claims 1, 2, and 5 and it is unclear if the limitations are different.
Claim(s) 6 recite(s) the language (emphasis added) “determining a way to obtain a first weight criticality for”, where “a first weight criticality” is already recited in claim 5 and it is unclear if the limitations are different.
Claim(s) 7 recite(s) the language (emphasis added) “determining a way to obtain a first weight criticality for”, where “a way” is already recited in claims 1, 2, 5, and 6 and it is unclear if the limitations are different.
Claim(s) 7 recite(s) the language (emphasis added) “determining a way to obtain a first weight criticality for”, where “a first weight criticality” is already recited in claims 5 and 6 and it is unclear if the limitations are different.
Claim(s) 8 recite(s) the language (emphasis added) “determining a way to obtain a second weight criticality of the plurality of memristor devices from the influence factor” and “determining a way to obtain a second weight criticality for each of the plurality of memristor devices from the second sub-influence factor” where “a way” is already disclosed in claim 1, and it is unclear if the two recitations of “a way” in claim 8 are different from each other, and different from the recitation in claim 1.
Claim(s) 8 recite(s) the language (emphasis added) “determining a way to obtain a second weight criticality of the plurality of memristor devices from the influence factor” and “determining a way to obtain a second weight criticality for each of the plurality of memristor devices from the second sub-influence factor”, where it is unclear if the limitations are different from one another.
Claim(s) 8 recite(s) the language (emphasis added) “each of the plurality of memristor devices from the second sub-influence factor”, where “the second sub-influence factor” lacks antecedent basis. The limitation “at least one second sub-influence factor” does no claim a particular “second sub-influence factor”.
Claim(s) 10 recite(s) the language (emphasis added) “in a neural unit layer of the neural network where the first computing memristor array”, where limitation “the neural network” lacks antecedent basis.
Claim(s) 14 recite(s) the language (emphasis added) “determining a way to obtain a second weight criticality for”, where “a way” is already recited in claims 1 and 8 and it is unclear if the limitations are different.
Claim(s) 14 recite(s) the language (emphasis added) “determining a way to obtain a second weight criticality for”, where “a second weight criticality” is already recited in claims 8 and it is unclear if the limitations are different.
Claim(s) 18 recite(s) the language (emphasis added) “obtaining a mapping relationship between the model parameters”, where “a mapping relationship” is already recited in claim 1 and it is unclear if the limitations are different.
Claim(s) 18 recite(s) the language (emphasis added) “to a plurality of memristor devices of the first computing memristor array”, where “a plurality of memristor devices” is already recited in claim 1.
Claim(s) 19 recite(s) the language (emphasis added) “an influence factor that determines a critical weight device, determining” and “the third computing module is configured to determine a critical weight device among”, where “a critical weight device” is disclosed twice and it is unclear if the limitations are different from one another.
Claim(s) 20 recite(s) the language (emphasis added) “for performing optimization processing on the first processing unit; wherein the optimization unit is configured to, based on the critical weight device, perform an optimization processing on the first processing unit according to the instruction”, where it is unclear if the two recitations of “optimization processing” are different from one another.
Claim(s) 24 recite(s) the language (emphasis added) “in a neural unit layer of the neural network where the first computing memristor array”, where limitation “the neural network” lacks antecedent basis.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 15, 16, 18-20, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strachan, US 20180373675 A1, in view of Linderman, US 20140172937 A1 and Jin, S. et al, A variation tolerant scheme for memristor crossbar based neural network designs via two-phase weight mapping and memristor programming, Future Generation Computer Systems, Volume 106, 2020, Pages 270-276 (hereafter references as NPL Jin).
As to claim 1, Strachan discloses a robustness processing method of a computing apparatus (see Strachan Fig 1 Ref 100), the computing apparatus comprising at least one processing unit (see Strachan Fig 1 Ref 110), the at least one processing unit comprising a first processing unit (see Strachan Fig 1 Ref 120), the first processing unit comprising a first computing memristor array (see Strachan Fig 1 Ref 126), the first computing memristor array comprising a plurality of memristor devices arranged in an array (see Strachan Fig 2).
Strachan does not appear to explicitly disclose the method comprises:
based on model parameters of a target algorithm model, obtaining a mapping relationship between the model parameters and the first computing memristor array; based on an influence factor that determines a critical weight device, determining a way to obtain a weight criticality of the plurality of memristor devices from the influence factor; obtaining an input set of the algorithm model, and determining a criticality value for each of the plurality of memristor devices according to the way; determining a critical weight device among the plurality of memristor devices according to the criticality value for each of the plurality of memristor devices; and based on the critical weight device, performing an optimization processing on the first processing unit.
Linderman discloses the method comprises:
based on model parameters of a target algorithm model (see Linderman Paras [0023] and [0049]), obtaining a mapping relationship (see Linderman Para [0023]) between the model parameters and the first computing memristor array (see Linderman Equation 16); based on an influence factor (see Linderman x(t+1) of Equation 16) that determines a characteristic, and obtaining an input set of the algorithm model (see Linderman Equation 19).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a computing apparatus, as disclosed by Strachan, may implement a mapping relationship, as disclosed by Linderman. The inventions are well known variants of resistive arrays configured to perform matrix operations, and the combination of inventions which produces predictable results is obvious and thus not patentable. Further evidence to the obviousness of their combination is Linderman’s attempt to improve the speed at which conductances can be mapped (see Linderman Para [0025]).
Strachan and Linderman do not appear to explicitly disclose an influence factor that determines a critical weight device, determining a way to obtain a weight criticality of the plurality of memristor devices from the influence factor; obtaining an input set of the algorithm model, and determining a criticality value for each of the plurality of memristor devices according to the way; determining a critical weight device among the plurality of memristor devices according to the criticality value for each of the plurality of memristor devices; and based on the critical weight device, performing an optimization processing on the first processing unit.
NPL Jin discloses an influence factor that determines a critical weight device (see NPL Jin Page 4, Col 1, Lines 33-46), determining a way (see NPL Jin Page 4, Col 1, Lines 33-46) to obtain a weight criticality of the plurality of memristor devices from the influence factor (see NPL Jin Page 4, Col 1, Lines 33); obtaining an input set of the algorithm model, and determining a criticality value for each of the plurality of memristor devices according to the way (see NPL Jin Equation 3); determining a critical weight device among the plurality of memristor devices according to the criticality value for each of the plurality of memristor devices; and based on the critical weight device, performing an optimization processing on the first processing unit (see NPL Jin Page 5, Col 1, Lines 2-47).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a computing apparatus, as disclosed by Strachan and Linderman, may implement a conductance mapping method, as disclosed by NPL Jin. The inventions are well known variants of resistive arrays configured to perform matrix operations, and the combination of inventions which produces predictable results is obvious and thus not patentable. Further evidence to the obviousness of their combination is NPL Jin’s attempt to improve prediction accuracy (see NPL Jin Page 2, Col 1, Lines 3-7).
As to claim 15, Strachan, Linderman, and NPL Jin disclose the method according to claim 1, wherein
based on the critical weight device, optimizing the first processing unit, comprising: optimizing the critical weight devices by using an averaging strategy; and/or optimizing the critical weight devices by using a re-refreshing strategy (see NPL Jin Fig 3).
As to claim 16, Strachan, Linderman, and NPL Jin disclose the method according to claim 1, wherein the method according to claim 1, wherein
determining a critical weight device among the plurality of memristor devices based on the criticality value for each of the plurality of memristor devices (see NPL Jin Page 4, Col 1, Lines 33-46), comprises: among the plurality of memristor devices, selecting a memristor device with a criticality value greater than a threshold corresponding to the first processing unit as the critical weight device (see NPL Jin Page 5, Col 1, Lines 2-47); or, among the plurality of memristor devices, selecting a device whose criticality value is within a first percentage of criticality values being sorted by size of the plurality of memristor devices as the critical weight device; or in each column of the plurality of memristor devices, selecting a device whose criticality value is within a second percentage of criticality values being sorted by size of the memristor device in the each column as the critical weight device.
As to claim 18, Strachan, Linderman, and NPL Jin disclose the method according to claim 1, wherein
obtaining a mapping relationship between the model parameters and the first computing memristor array (see Linderman Para [0023]), comprises:
obtaining the model parameters through compiler deployment and division (see NPL Jin Page 4, Col 1, Lines 33-46), and mapping a portion of the model parameters corresponding to the first computing memristor array to a plurality of memristor devices of the first computing memristor array (see NPL Jin Page 5, Col 1, Lines 2-47).
As to claim 19, Strachan, Linderman, and NPL Jin disclose a computing apparatus (see Strachan Fig 1 Ref 100), comprising:
a first computing module, a second computing module, a third computing module (see Strachan Fig 1 Ref 112) and an in-memory computing module (see Strachan Fig 1 Ref 130 and Fig 3 Ref 300; In-memory computation as understood in the art does not appear to be explicitly disclosed in the specification and broadest reasonable interpretation has been applied.), wherein
the in-memory computing module comprises at least one processing unit (see Strachan Fig 1 Ref 110) and an optimization unit (see Strachan Fig 3 Refs 303 and 304), the at least one processing unit comprises a first processing unit (see Strachan Fig 1 Ref 120), the first processing unit comprises a first computing memristor array (see Strachan Fig 1 Ref 126), and the first computing memristor array comprises a plurality of memristor devices arranged in an array (see Strachan Fig 2);
the first computing module is configured to, based on model parameters of a target algorithm model (see Linderman Paras [0023] and [0049]), obtain a mapping relationship (see Linderman Para [0023]) between the model parameters and the first computing memristor array (see Linderman Equation 16), and based on an influence factor (see Linderman x(t+1) of Equation 16) that determines a critical weight device (see NPL Jin Page 4, Col 1, Lines 33-46), determine a way (see NPL Jin Page 4, Col 1, Lines 33-46) to obtain a weight criticality of the plurality of memristor devices from the influence factor (see NPL Jin Page 4, Col 1, Lines 33-46);
the second computing module is configured to, obtain an input set of the algorithm model (see Linderman Equation 19), and determine a criticality value (see NPL Jin Equation 3) for each of the plurality of memristor devices according to the way; the third computing module is configured to determine a critical weight device (see NPL Jin Page 4, Col 1, Lines 33-46) among the plurality of memristor devices according to the criticality value for each of the plurality of memristor devices; the optimization unit is configured to perform optimization processing on the first processing unit based on the critical weight device (see NPL Jin Page 5, Col 1, Lines 2-47).
As to claim 20, Strachan, Linderman, and NPL Jin disclose a computing apparatus, comprising:
a first computing sub-apparatus (see Strachan Fig 1 Ref 100) and an in-memory computing module (see Strachan Fig 1 Ref 130 and Fig 3 Ref 300; In-memory computation as understood in the art does not appear to be explicitly disclosed in the specification and broadest reasonable interpretation has been applied.), wherein
the in-memory computing module comprises at least one processing unit (see Strachan Fig 1 Ref 110) and an optimization unit (see Strachan Fig 3 Refs 303 and 304), the at least one processing unit comprises a first processing unit (see Strachan Fig 1 Ref 120), the first processing unit comprises a first computing memristor array, and the first computing memristor array comprises a plurality of memristor devices arranged in an array (see Strachan Fig 2);
the first computing sub-apparatus comprises: a processor (see Strachan Fig 1 Ref 112) and a memory (see Strachan Fig 1 Ref 150), wherein
the memory stores a computer executable program, and the computer executable program, when executed by the processor (see Strachan Fig 1 Ref 150 and Para [0020]), is configured to implement the following method:
based on model parameters of a target algorithm model (see Linderman Paras [0023] and [0049]), obtaining a mapping relationship (see Linderman Para [0023]) between the model parameters and the first computing memristor array (see Linderman Equation 16); based on an influence factor (see Linderman x(t+1) of Equation 16) that determines a critical weight device (see NPL Jin Page 4, Col 1, Lines 33-46), determining a way (see NPL Jin Page 4, Col 1, Lines 33-46) to obtain a weight criticality of the plurality of memristor devices from the influence factor (see NPL Jin Page 4, Col 1, Lines 33-46);
obtaining an input set of the algorithm model (see Linderman Equation 19), and determine a criticality value for each of the plurality of memristor devices according to the way (see NPL Jin Equation 3); determining a critical weight device among the plurality of memristor devices according to the criticality value for each of the plurality of memristor devices (see NPL Jin Page 5, Col 1, Lines 2-47); and
based on the critical weight device, providing an instruction for performing optimization processing on the first processing unit; wherein
the optimization unit is configured to, based on the critical weight device, perform an optimization processing on the first processing unit according to the instruction (see NPL Jin Page 5, Col 1, Lines 2-47).
As to claim 23, Strachan, Linderman, and NPL Jin disclose the computing apparatus according to claim 19, wherein
the in-memory computing module further comprises a critical weight control unit, which is configured to select and process the critical weight device (see NPL Jin Fig 3).
Response to Arguments
Applicant's arguments filed 02/05/2026 have been fully considered but they are partially persuasive.
New art has been provided which reads on the claimed subject matter. Applicant has not overcome the previous 112 rejections and the claim language needs to be further clarified so the scope of the invention is understandable to one of ordinary skill in the art.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
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/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 08/03/2026
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