DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by PCT.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 07/08/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation "a data line, which is coupled to a sub-pixel driving circuit" in line 7. There is a previous recitation of both “a data line” and “the sub-pixel driving circuit” in claim 18, rendering it unclear whether “a data line, which is coupled to a sub-pixel driving circuit” refers to a same or distinct set of the aforementioned components. Therefore, for Examination purposes, "a data line, which is coupled to a sub-pixel driving circuit" has been interpreted as --- the data line, which is coupled to the sub-pixel driving circuit" --- however, this edit may be altered if Applicant intends otherwise.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shang (U.S. PG Pub No US2022/0285458A1).
Regarding claim 1, Shang teaches a display substrate [0040], comprising:
a base substrate (not shown, pixel units and circuitry arranged atop substrate) [0007], and
a compensation signal line (901 comprising 906) fig. 3 [0086] and a plurality of sub-pixels [0040-0043] (comprising respective circuitry units; one subpixel featured in fig. 3) on the base substrate [0007];
wherein the sub-pixel [0040-0043] comprises a sub-pixel driving circuit (comprising T3, Cst 2) fig. 3 [0041, 0043, 0061];
the sub-pixel driving circuit comprises a driving transistor (T3) fig. 3 [0043] and a compensation structure (Cst 2 coupled to 901) fig. 3 [0061];
the driving transistor (T3) comprises a driving active pattern (active film layer comprising 103 pg) fig. 4 [0056, 0061] (see annotated fig. 3 below) and a gate electrode (203g) fig. 3 [0061], and an overlapping portion between an orthographic projection of the driving active pattern (active film layer comprising 103 pg) onto the base substrate [0007] and an orthographic projection of the gate electrode (203g) onto the base substrate [0007], serves as a driving channel portion (103 pg portion) (see annotated fig. 3 below);
the compensation structure (Cst 2) fig. 3 [0061] is coupled to [0061] the corresponding compensation signal line (901), and an orthographic projection of the compensation structure (Cst 2) fig. 3 [0061] onto the base substrate [0007] is located at a (left) side of an orthographic projection of the driving channel portion (103 pg portion) onto the base substrate [0007].
[AltContent: rect][AltContent: textbox (CP2)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (EP-II)][AltContent: arrow][AltContent: arrow][AltContent: textbox (EP-I)][AltContent: arrow][AltContent: textbox (EP4)][AltContent: arrow][AltContent: arrow][AltContent: textbox (Symmetry-axis)][AltContent: connector][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: textbox (EP5)][AltContent: textbox (CP1)][AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: textbox (MP)][AltContent: rect][AltContent: arrow][AltContent: textbox (EP2)][AltContent: textbox (EP1)][AltContent: arrow][AltContent: textbox (Driving
Channel portion 103pg of active film )][AltContent: arrow][AltContent: textbox (Active film )][AltContent: rect]
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Annotated fig. 3 of Shang
Regarding claim 2, Shang teaches the display substrate [0040] of claim 1. Shang also teaches wherein the compensation structure (Cst 2) fig. 3 [0061] comprises a first compensation pattern (CP1) see annotated fig. 3 above [0061] and the first compensation pattern (CP1 of Cst 2) is coupled to [0061] the corresponding compensation signal line (901).
Regarding claim 3, Shang teaches the display substrate [0040] of claim 2. Shang also teaches wherein the first compensation pattern (CP1 of Cst 2) see annotated fig. 3 above [0061] comprises a first main body portion (MP) and a first extension portion (EP-I comprising EP1, EP2) coupled to each other (see annotated fig. 3 above);
the first main body portion (MP) is coupled to [0061] the corresponding compensation signal line (901) fig. 3 [0061], and an orthographic projection of at least a portion of the first extension portion (EP-I) onto the base substrate [0007] is (partially) between an orthographic projection of the first main body portion (MP) onto the base substrate [0007] and the (bottom, left corner of) orthographic projection of the gate electrode (203g) fig. 3 [0061] of the driving transistor (T3) fig. 3 [0043] onto the base substrate [0007].
Regarding claim 4, Shang teaches the display substrate [0040] of claim 3. Shang also teaches wherein the first extension portion (EP-I) comprises a first portion (EP1) and a second portion (EP2) (see annotated fig. 3 above);
the first portion (EP1) and the second portion (EP2) are arranged in a first (y) direction;
the first portion (EP1) is respectively coupled to (electrically coupled through Cst 2 material metal material) [0059-0061] the first main body portion (MP) and the second portion (EP2) (electrically coupled through Cst 2 material metal material) [0059-0061]; and
in a direction (x) perpendicular to the first direction (y), a (total) width of the first portion (EP1) is less than a (total) width of the second portion (as defined in annotated fig. 3 above).
Regarding claim 5, Shang teaches the display substrate [0040] of claim 4. Shang also teaches wherein the first extension portion (EP-I) further comprises a third portion (EP-II = EP4 with EP5);
the third portion (EP4 with EP5) is coupled to (electrically coupled through Cst 2 material metal material) [0059-0061] the second portion (EP2);
the third portion (EP4 with EP5) extends in a second direction (x), and the second direction (x) intersects with the first direction(y) (see annotated fig. 2 above).
Regarding claim 6, Shang teaches the display substrate [0040] of claim 3. Shang also teaches wherein the first compensation pattern (CP1 of Cst 2) see annotated fig. 3 above [0061] further comprises a second extension portion (EP-II = EP4 with EP5) coupled to (electrically coupled through Cst 2 material metal material) [0059-0061] the first main body portion (MP), and an orthographic projection of the first extension portion (EP) onto the base substrate [0007] is (vertically) between an orthographic projection of the second extension portion (EP 4 with EP5) onto the base substrate [0007] and the orthographic projection of the gate electrode (203g) fig. 3 [0061] of the driving transistor (T3) fig. 3 [0043] onto the base substrate [0007] (see annotated fig. 3 above).
Regarding claim 7, Shang teaches the display substrate [0040] of claim 6. Shang also teaches wherein the second extension portion (EP-II) comprises a fourth portion (EP4) and a fifth portion (EP5);
the fourth portion (EP4) and the fifth portion (EP5) are arranged in a first (y) direction;
the fourth portion (EP4) is respectively coupled (electrically coupled through Cst 2 material metal material) [0059-0061] to the first main body portion (MB) and the fifth portion (EP5); and
in a direction (x) perpendicular to the first (y) direction, a width of the fourth portion (EP4) is less than a width of the fifth portion (EP5) (as defined in annotated fig. 3 above)
Regarding claim 8, Shang teaches the display substrate [0040] of claim 6. Shang also teaches wherein the first extension portion (EP-I) and the second extension portion (EP-II) are symmetrically arranged (are defined as having identical shapes and glide-reflectional symmetry) about a symmetry axis (see annotated fig. 3 above), and the symmetry (horizontal) axis is between the first extension portion (EP) and the second extension portion (EP3 comprising EP4, Ep5) and extends in a first (x) direction (see annotated fig. 3 above).
Regarding claim 16, Shang teaches the display substrate [0040] of claim 14. Shang also teaches wherein the first compensation pattern (CP1 of Cst 2) fig. 3 [0061] comprises (refer to annotated fig. 3-II of Shang below) a second main body portion (MP) and a third extension portion (EP-II) coupled to (electrically coupled through Cst 2 material metal material) [0059-0061] each other;
the second main body portion (MP) is coupled to [0049] (electrically coupled through Cst 2 material metal material) [0059-0061] the corresponding compensation signal line (901 comprising 906) fig. 3 [0086]; and
an orthographic projection of the second main body portion (MP) onto the base substrate [0007] is between (vertically) an orthographic projection of the third extension portion (EP-I) onto the base substrate [0007] and the orthographic projection of the (upper side of) gate electrode (203g) fig. 3 [0061] of the driving transistor (T3) fig. 3 [0043] onto the base substrate [0007] (as defined in annotated fig. 3-II of Shang below).
[AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: textbox (EP-II)][AltContent: arrow][AltContent: textbox (EP4)][AltContent: arrow][AltContent: arrow][AltContent: connector][AltContent: rect][AltContent: rect][AltContent: textbox (EP5)][AltContent: textbox (CP1)][AltContent: arrow][AltContent: rect][AltContent: textbox (MP)][AltContent: arrow][AltContent: textbox (Driving
Channel portion 103pg of active film )][AltContent: arrow][AltContent: textbox (Active film )][AltContent: rect]
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Annotated fig. 3-II of Shang
Regarding claim 17, Shang teaches the display substrate [0040] of claim 2. Shang also teaches wherein the display substrate further comprises a first scanning line (902) fig. 3 [0050, 0052];
the sub-pixel driving circuit (comprising T3, Cst 2) fig. 3 [0041, 0043, 0061] further comprises a compensation transistor (T 5) fig. 3 [0046];
a gate electrode (205 g) fig. 3 [0046] of the compensation transistor (T 5) is coupled to the corresponding first scanning line (902) (902 and T 5 commonly coupled through active layer material of T1-T7 [see fig. 4, 0056, 0046-0048]);
a first electrode (drain electrode D5) [0046] of the compensation transistor (T 5) is coupled to a second electrode (source electrode S3) [0046] of the driving transistor (T3) fig. 3 [0043], and a second electrode (source electrode S5) [0046] of the compensation transistor (T 5) is coupled to the gate electrode (203g) fig. 3 [0061] of the driving transistor (T3) fig. 3 [0043] (respective transistor components commonly coupled through active layer material of T1-T7 [see fig. 4, 0056, 0044-0046]);
the first scanning line (902) comprises at least a portion extending (primarily horizontally) in a second direction (x); and
in a layout region of the same sub-pixel [same cross-section of fig. 3], the first scanning line (902) comprises a protrusion (vertical protrusion downward from 902) which protrudes in a direction (vertically) away from the first compensation pattern (CP1 of Cst 2) fig. 3 [0061];
an orthographic projection of the protrusion onto the base substrate [0007] and an orthographic projection of the first compensation pattern (CP1 of Cst 2) onto the base substrate [0007] are arranged along a first (y) direction;
an orthographic projection of the first scanning line (902) onto the base substrate [0007] does not overlap the orthographic projection of the first compensation pattern (CP1 of Cst 2) onto the base substrate [0007], and the first direction (y) intersects with the second direction (x).
Regarding claim 18, Shang teaches the display substrate [0040] of claim 2. Shang also teaches wherein the display substrate further comprises a data line (908) fig. 3 [0042];
the sub-pixel driving circuit (comprising T3, Cst 2) fig. 3 [0041, 0043, 0061] further comprises a data writing transistor (T 4) fig. 3 [0045];
a first electrode (source electrode S 4) fig. 3 [0045] of the data writing transistor (T 4) is coupled to the corresponding data line (908), and a second electrode (drain electrode D4) fig. 3 [0045] of the data writing transistor (T 4) is coupled to a first electrode of the driving transistor (T3) fig. 3 [0043];
an orthographic projection of the (right half of) first compensation pattern (CP1 of Cst 2) fig. 3 [0061] on to the base substrate [0007] is (horizontally) between the orthographic projection of the gate electrode (203g) fig. 3 [0061] of the driving transistor (T3) fig. 3 [0043] onto the base substrate [0007] and an orthographic projection of the data line (908), which is coupled to [0045] the sub-pixel driving circuit (comprising T3, Cst 2, T4) fig. 3 [0041, 0043, 0061] to which the first compensation pattern (CP1 of Cst 2) belongs, onto the base substrate [0007].
Regarding claim 19, Shang teaches the display substrate [0040] of claim 2. Shang also teaches wherein there is a first distance (distance of ~0) between (portions of) an orthographic projection of the first compensation pattern (CP1 of Cst 2) onto the base substrate [0007] and the orthographic projection of the gate electrode (203g) fig. 3 [0061] of the driving transistor (T3) fig. 3 [0043] onto the base substrate [0007], and the first distance is less than or equal to 7 micrometers (approximately 0 micrometers because 203g and Cst 2 overlap).
Regarding claim 20, Shang teaches a display device (display panel) [see fig. 3, 0040], comprising a display substrate [0040] (comprising subpixel circuitry shown in fig. 3),
wherein the display substrate [0040] comprises:
a base substrate (not shown, pixel units and circuitry arranged atop substrate) [0007], and a compensation signal line (901 comprising 906) fig. 3 [0086] and a plurality of sub-pixels [0040-0043] (comprising respective circuitry units; one subpixel featured in fig. 3) on the base substrate [0007];
wherein the sub-pixel [0040-0043] comprises a sub-pixel driving circuit (comprising T3, Cst 2) fig. 3 [0041, 0043, 0061]; the sub-pixel driving circuit (comprising T3, Cst 2) comprises a driving transistor (T3) fig. 3 [0043] and a compensation structure (Cst 2 coupled to 901) fig. 3 [0061]; the driving transistor (T3) comprises a driving active pattern (active film layer comprising 103 pg) fig. 4 [0056, 0061] (see annotated fig. 3 below) and a gate electrode (203g) fig. 3 [0061], and an overlapping portion between an orthographic projection of the driving active pattern (active film layer comprising 103 pg) onto the base substrate [0007] and an orthographic projection of the gate electrode (203g) onto the base substrate [0007], serves as a driving channel portion (103 pg portion) (see annotated fig. 3 below)
the compensation structure (Cst 2) fig. 3 [0061] is coupled to [0061] the corresponding compensation signal line (901), and an orthographic projection of the compensation structure (Cst 2) fig. 3 [0061] onto the base substrate [0007] is located at a (left) side of an orthographic projection of the driving channel portion (103 pg portion) onto the base substrate [0007].
[AltContent: rect][AltContent: textbox (CP2)][AltContent: arrow][AltContent: arrow][AltContent: arrow][AltContent: textbox (EP-II)][AltContent: arrow][AltContent: arrow][AltContent: textbox (EP-I)][AltContent: arrow][AltContent: textbox (EP4)][AltContent: arrow][AltContent: arrow][AltContent: textbox (Symmetry-axis)][AltContent: connector][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: rect][AltContent: textbox (EP5)][AltContent: textbox (CP1)][AltContent: arrow][AltContent: rect][AltContent: arrow][AltContent: arrow][AltContent: textbox (MP)][AltContent: rect][AltContent: arrow][AltContent: textbox (EP2)][AltContent: textbox (EP1)][AltContent: arrow][AltContent: textbox (Driving
Channel portion 103pg of active film )][AltContent: arrow][AltContent: textbox (Active film )][AltContent: rect]
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Annotated fig. 3 of Shang
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Shang (U.S. PG Pub No US2022/0285458A1), as applied in claim 3 above, in view of Lee (U.S. PG Pub No US2016/0070145A1).
Regarding claim 9, Shang teaches the display substrate [0040] of claim 3. However, Shang does not explicitly disclose wherein the first compensation pattern (Cst 2) fig. 3 [0061] and the driving active pattern (active film layer comprising 103 pg) fig. 4 [0056, 0061] are in a same layer of a same material (relevant cross-sectional view not shown).
Lee teaches a display substrate [see fig. 8, 0064] wherein the first compensation pattern (CP2b) fig. 8 [0064] and the driving active pattern (A) fig. 8 [0065] are in a same layer (PAS1) fig. 8 [0057] of a same material (PAS1).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have explicitly disposed the compensation pattern(s) [0064] uniformly with other components such as the transistor active layer [0061, 0065] on the same level in the same layer [0057] in order to improve the uniformity of the disposal of the compensation patterns in the display [0069] to help reduce parasitic capacitance between components [0070], as taught by Lee.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Shang (U.S. PG Pub No US2022/0285458A1), as applied in claim 2 above, in view of Lee (U.S. PG Pub No US2011/0095294A1).
Regarding claim 14, Shang teaches the display substrate [0040] of claim 2. However, Shang does not explicitly disclose wherein the first compensation pattern (Cst 2) fig. 3 [0061] and the gate electrode (203g) fig. 3 [0061] of the driving transistor (T3) fig. 3 [0043] are in a same layer of a same material.
Lee teaches a transistor substrate applicable to displays [see fig. 3, 0005, 0050-0052] wherein the first compensation pattern (125) fig. 3 [0052] and the gate electrode (124a) fig. 3 [0052] of the driving transistor [0051] are in a same layer (140) fig. 3 [0056] of a same material (SiN layer 140) [0056].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have explicitly disposed the compensation pattern(s) [0052] at the same level and in in the same insulating material layer as the gate electrode(s) [0050-0052, 0056] in order to enhance the alignment of these components [0013, 0053] in order to reduce possible parasitic capacitance in the display [0071-0072], as taught by Lee.
Regarding claim 15, Shang teaches the display substrate [0040] of claim 2. However, Shang does not explicitly disclose wherein the display substrate [0007, 0040] further comprises a second gate metal layer (205 g) fig. 3 [0046].
However, Shang does not explicitly disclose and the first compensation pattern (Cst 2) fig. 3 [0061] and the second gate metal layer are in a same layer of a same material.
Lee teaches a transistor substrate applicable to displays [see fig. 3, 0005, 0050-0052] wherein the first compensation pattern (125) fig. 3 [0052] and the second gate metal layer (124b) fig. 3 [0052] are in a same layer (140) fig. 3 [0056] of a same material (SiN layer 140) [0056].
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have explicitly disposed the compensation pattern(s) [0052] at the same level and in in the same insulating material layer as the gate electrode(s) [0050-0052, 0056] in order to enhance the alignment of these components [0013, 0053] in order to reduce possible parasitic capacitance in the display [0071-0072], as taught by Lee.
Allowable Subject Matter
Claims 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 10 is objected to as containing allowable subject matter because the prior art of record neither anticipates nor renders obvious the claimed limitation(s) “an orthographic projection of the second compensation pattern onto the base substrate at least partially overlaps with the orthographic projection of the first extension portion onto the base substrate; and/or, the orthographic projection of the second compensation pattern onto the base substrate at least partially overlaps with an orthographic projection of the second extension portion of the first compensation pattern onto the base substrate.” in the context of claim 10, dependent upon claim 9, dependent upon claim 3, dependent upon claim 2, dependent upon claim 1. Claims 11-13 are also objected to as containing allowable subject matter by virtue of their dependency on claim 10.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Remaining references made available on the PTO-892 form are considered relevant to the present disclosure because they all feature display devices with compensation patterns.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEAN AYERS WINTERS whose telephone number is (571)270-3308. The examiner can normally be reached Monday - Friday 10:30 am - 7:00 pm (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEAN AYERS WINTERS/Examiner, Art Unit 2892 02/26/2026
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892