DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 5, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 4-20 are objected to because of the following informalities:
Note: Any suggestions to amend the claims in this section are to address the objections and do not necessarily address any rejections that may be made subsequently in the Office Action.
Regarding claim 4: The expression comprising A before B does not make sense in English. Furthermore, one of A and B or both being signals in a claim that is claiming structure causes further problems. Claims 5-13 depend on claim 4. In light of FIG. 2 of the application, Examiner believes that Applicant intended to write the following:
A memory core complex comprising:
a plurality of memory banks, wherein each memory bank includes a two- dimensional array of memory cells and a memory cell access circuit;
a plurality of local bit lines extending vertically and connecting all memory cells in the two-dimensional array;
a plurality of word lines (WL) extending horizontally and connecting all memory cells in the two-dimensional array; and
at least one banked sense amplifier circuit, wherein the banked sense amplifier circuit is connected to a global bit line (GBL) of the memory core complex, wherein the plurality of local bit lines are inputs to the at least one banked sense amplifier circuit, and wherein the at least one banked sense amplifier circuit further comprises :
a switch arranged between the sense amplifier and ground, and the switch receives a sense signal
.
Regarding claim 14: The expression comprising A before B does not make sense in English. Furthermore, one of A and B or both being signals in a claim that is claiming structure causes further problems. Claims 15-20 depend on claim 14. In light of FIG. 2 of the application, Examiner believes that Applicant intended to write the following:
A memory c ore complex comprising:
a plurality of double memory banks, wherein each double memory bank comprises two memory banks, wherein each memory bank includes a two- dimensional array of memory cells and a memory cell access circuit;
a plurality of local bit lines extending vertically and connecting all memory cells in the two-dimensional array;
a plurality of word lines (WL) extending horizontally and connecting all memory cells in the two-dimensional array; and
a banked sense amplifier circuit, wherein the banked sense amplifier circuit is connected to a global bit line (GBL) of the memory core complex, wherein the plurality of local bit lines are inputs to the at least one banked sense amplifier circuit, and wherein the at least one banked sense amplifier circuit further comprises :
a switch arranged between the sense amplifier and ground, and the switch receives a sense signal
.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 4-9, 12-18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Roy (US 4,926,384).
Regarding claim 4: Roy teaches a memory core complex (50 in FIG. 5) comprising:
a plurality of memory banks (blocks BLK in FIG. 5), wherein each memory bank includes a two-dimensional array (block) of memory cells (each block 70 or 72 comprises columns as seen in FIG. 6, and each column comprises memory cells as seen in FIG. 3 or FIG. 8) and a memory cell access circuit (MUXs 78 and/or 78’);
a plurality of local bit lines (76 in FIG. 6) extending vertically (the horizontal direction in each of FIG. 5, FIG. 6, FIG. 7 and FIG. 8 when reading the figure label at the bottom of the page) and connecting all memory cells in the two-dimensional array (as seen in FIG. 8; a bit line pair BL and BLB connect a column of memory cells);
a plurality of word lines (WL) extending horizontally (ROW lines running vertically in each of FIG. 5, FIG. 6, FIG. 7 and FIG. 8) and connecting all memory cells in the two-dimensional array; and
at least one banked sense amplifier circuit (64 in each of FIG. 5, FIG. 6, FIG. 7 and FIG. 14), wherein the banked sense amplifier circuit is connected to a global bit line (GBL) (one or both of io and iob signals in FIG. 14 from each amplifier may be referred to as a global bit line) of the memory core complex, wherein the plurality of local bit lines are inputs to the at least one banked sense amplifier circuit (as illustrated in the cited figures), and wherein the at least one banked sense amplifier circuit further comprising:
a ground (see ground connection symbol at bottom of FIG. 14); and
a sense signal (SA) directly before the ground (connected to a transistor that is between ground and the rest of the sense amplifier 64).
Regarding claim 5: Roy teaches the memory core complex according to claim 4, wherein the banked sense amplifier circuit is configured to sense at least one local bit line (a local bit line pair from either a left block or a right block as seen in FIG. 7) out of the local bit lines of two neighboring memory banks (a left block and a right block) out of the plurality of memory banks to be used as independent read paths (independently read based on BSML and BSMR selection signals; FIG. 12).
Regarding claim 6: Roy teaches the memory core complex according to claim 4, wherein the banked sense amplifier is configured to sense at least one local bit line pair out of local bit line pairs (a local bit line pair from either a left block or a right block as seen in FIG. 7) of two neighboring memory banks (a left block and a right block) out of the plurality of memory banks to be used as independent read paths (independently read based on BSML and BSMR selection signals; FIG. 12).
Regarding claim 7: Roy teaches the memory core complex according to claim 4, wherein at least one multiplexer is provided in the at least one memory bank per the verticality associated with local bit lines of two neighboring memory banks out of the plurality of memory banks (see MUXs 78 and 78’ in FIG. 6 and FIG. 7).
Regarding claim 8: Roy (FIG. 7 and FIG. 14) teaches the memory core complex according to claim 7, wherein the banked sense amplifier circuit is logically located between the at least one multiplexer and the global bit line (GBL).
Regarding claim 9: Roy (FIG. 7 and FIG. 14) teaches the memory core complex according to claim 7, wherein the at least one multiplexer is configured to transfer the local bit lines to the banked sense amplifier circuit, wherein the transfer of the local bit lines to the banked sense amplifier circuit is driven by a local read enable line (mux select line CRD).
Regarding claim 12: Roy teaches the memory core complex according to claim 4, wherein two memory banks out of the plurality of memory banks are arranged in a double memory bank (a set of left memory blocks and a set of right memory blocks as seen in FIG. 5).
Regarding claim 13: Roy teaches the memory core complex according to claim 12, wherein at least one multiplexer (see MUXs 78 and 78’ in FIG. 6 and FIG. 7) is provided in the double memory bank per the verticality associated with at least one local bit line of each of two neighboring memory banks in the double memory bank.
Regarding claim 14: Roy teaches a memory core complex (50 in FIG. 5) comprising:
a plurality of double memory banks (FIG. 5 may be divided into a plurality of double memory banks, each bank comprising at least one left memory block and at least one right memory block), wherein each double memory bank comprises two memory banks (a left and right memory block), wherein each memory bank includes a two-dimensional array of memory cells (a block) and a memory cell access circuit (MUX 78 or 78’; see FIG. 6 and FIG. 7);
a plurality of local bit lines (76 in FIG. 6) extending vertically (the horizontal direction in each of FIG. 5, FIG. 6, FIG. 7 and FIG. 8 when reading the figure label at the bottom of the page) and connecting all memory cells in the two-dimensional array (as seen in FIG. 8; a bit line pair BL and BLB connect a column of memory cells);
a plurality of word lines (WL) extending horizontally (ROW lines running vertically in each of FIG. 5, FIG. 6, FIG. 7 and FIG. 8) and connecting all memory cells in the two-dimensional array; and
a banked sense amplifier circuit (64 in each of FIG. 5, FIG. 6, FIG. 7 and FIG. 14), wherein the banked sense amplifier circuit is connected to a global bit line (GBL) (one or both of io and iob signals in FIG. 14 from each amplifier may be referred to as a global bit line) of the memory core complex, wherein the plurality of local bit lines are inputs to the at least one banked sense amplifier circuit (as illustrated in the cited figures), and wherein the at least one banked sense amplifier circuit further comprising:
a ground (see ground connection symbol at bottom of FIG. 14); and
a sense signal (SA) directly before the ground (connected to a transistor that is between ground and the rest of the sense amplifier 64).
Regarding claim 15: Roy teaches the memory core complex according to claim 14, wherein the banked sense amplifier circuit is configured to sense at least one local bit line-pair (a local bit line pair from either a left block or a right block as seen in FIG. 7) out of the local bit line-pairs of two neighboring memory banks (a left block and a right block) of a double memory bank out of the plurality of double memory banks to be used as independent read paths (independently read based on BSML and BSMR selection signals; FIG. 12).
Regarding claim 20: Roy teaches the memory core complex according to claim 15, wherein in the banked sense amplifier circuit ports of bit lines not used for the sensing process (for example when a left memory block is selected for reading, a right memory block is not selected for reading) are configured as additional read ports (to be used as read ports at another time when the right memory block is selected for reading and the left memory block is not selected).
Regarding claim 16: Roy teaches the memory core complex according to claim 14, wherein at least one multiplexer is provided in the at least one memory bank per the verticality associated with local bit lines of two neighboring memory banks out of the plurality of memory banks (see MUXs 78 and 78’ in FIG. 6 and FIG. 7).
Regarding claim 17: Roy (FIG. 7 and FIG. 14) teaches the memory core complex according to claim 16, wherein the banked sense amplifier circuit is logically located between the at least one multiplexer and the global bit line (GBL).
Regarding claim 18: Roy (FIG. 7 and FIG. 14) teaches the memory core complex according to claim 16, wherein the at least one multiplexer is configured to transfer the local bit lines to the banked sense amplifier circuit, wherein the transfer of the local bit lines to the banked sense amplifier circuit is driven by a local read enable line (mux select line CRD).
.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) s 1-2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roy (US 4,926,384) in view of Wu et al. (US 2023/0420041).
Regarding claim 1: Roy (FIGs. 5-8 and FIG. 14; columns, 6, 7, and 13 ) teaches a banked sense amplifier circuit (sense amp 64) for a memory core complex (memory 50; a memory core comprising memory blocks BLK to the right and to the left as seen in FIG. 5), being configured to sense at least one local bit line out of horizontally-oriented local bit lines of two neighboring memory banks out of a plurality of memory banks of the memory core complex to be used as independent read paths (a read path from the left memory block or the right memory block is selected by BSML or BSMR signals), wherein the banked sense amplifier circuit is connected to a global bit line (GBL) (one or both of io and iob signals in FIG. 14 from each amplifier may be referred to as a global bit line) of the memory core complex, and wherein the banked sense amplifier circuit includes a sense signal (SA) provided on a cycle basis (on a read cycle basis; see FIG. 12).
Roy does not specifically teach the sense signal is from a processor.
Wu teaches an SRAM based memory, wherein a sense amplifier enable signal SAE is from a processor (see “signal SAE from a controller” in [0032] and see “For instance, the related functions of the memory control circuit and/or the memory controller may be implemented in one or a plurality of controllers, a micro-controller, a micro-processor, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), and/or various logic blocks, modules, and circuits in other processing units” in [0080]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Wu into the device and/or method of Roy in a manner such that the sense signal SA would be from a processor used a controller for the memory. The motivation to do so would have been to use circuitry that was already known to be suitable for providing control signals, such as a sense amplifier enable signal, to an SRAM memory as exemplified by Wu.
Regarding claim 2: Roy as modified above teaches the banked sense amplifier circuit according to claim 1, being configured to sense at least one local bit line pair (a bit line pair selected from a right block , such as BLR7 and BLBR7 in FIG. 7, or a bit line pair selected from a left block, such as BLL7 and BLBL7) out of local bit line pairs of two neighboring memory banks (blocks or set of blocks) out of the plurality of memory banks of the memory core complex to be used as independent read paths (since signals BSML and BSMR are independent signals along with CRD signals all used to select an independent read path from a left block or a right block).
Claim(s) 10 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roy (US 4926384) in view of Liaw (US 2010/0259971).
Regarding claim 10: Roy teaches the memory core complex according to claim 4, wherein an input/output device (DATA OUT BUFFER in FIG. 14) is provided.
Roy does not specifically teach the input/out device comprising output drivers for transferring the global bit lines (GBL) to output lines.
Liaw (FIG. 7; [0032]) teaches an SRAM memory comprising an input/output device is provided comprising output drivers (Global_SA1:m) for transferring global bit lines (R-GBL1:m) to output lines (the output lines of the Global_SA1:m for amplifying the signals on the global bit lines and outputting the amplified signals).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Liaw into Roy in a manner such that the data out buffer of Roy would comprise output drivers like that of Liaw (Global_SA1 to Sam) for transferring the data onto output lines. The motivation to do so would have been to provide driver circuitry to amplify and output the bit line signals like that of Liaw so that the data signals io and iob per amplifier 64 may be driven to an external device.
Regarding claim 19: Roy teaches the memory core complex according to claim 14, wherein an input/output device (DATA OUT BUFFER in FIG. 14) is provided.
Roy does not specifically teach the input/output device comprises an output driver for transferring the global bitline (GBL) to an output line.
Liaw (FIG. 7; [0032]) teaches an SRAM memory comprising an input/output device is provided comprising output drivers (Global_SA1:m) for transferring global bit lines (R-GBL1:m) to output lines (the output lines of the Global_SA1:m for amplifying the signals on the global bit lines and outputting the amplified signals).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Liaw into Roy in a manner such that the data out buffer of Roy would comprise output drivers like that of Liaw (Global_SA1 to Sam) for transferring the data onto output lines so that the input/output device would comprise an output driver for transferring a global bitline (GBL), io line or iob line in FIG. 14, to an output line. The motivation to do so would have been to provide driver circuitry to amplify and output the bit line signals like that of Liaw so that the data signals io and iob per amplifier 64 may be driven to an external device.
Response to Arguments
Applicant’s arguments with respect to the pending claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827