CTNF 18/581,186 CTNF 88433 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification The specification submitted 2/19/2024 has been accepted by the examiner. Drawings The drawings submitted on 2/19/2024 have been accepted by the examiner. Information Disclosure Statement The information disclosure statement (IDS) submitted on 2/19/2024 has been considered by the examiner. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 3, 6-7, 9, 11-13, 16-17, and 19 are rejected under 35 U.S.C. 102( a)(1)/(a)(2 ) as being anticipated by Shin (US # 20230123234) . Regarding Claim 1 , Shin (US # 20230123234) teaches a memory device (see Figs. 12-13 and corresponding text) comprising: a gate electrode (560); a channel layer (515) spaced apart from the gate electrode; a charge trap layer (535) between the gate electrode and the channel layer; and a two-dimensional material layer (540) between the charge trap layer and the gate electrode, wherein the two-dimensional material layer includes a material having an electron affinity of less than 1 eV ([0064] teaches 2D materials for example, BN, h-BN, MnO.sub.2, MoO.sub.3, GaSe, Ga.sub.2N.sub.3, or As.sub.2S.sub.3; h-BN for example has a less-than-zero electron affinity, at about −0.5 eV). Regarding Claim 3 , Shin teaches the memory device of claim 1, wherein the two-dimensional material layer comprises an insulator material ([0064]). Regarding Claim 6 , Shin teaches the memory device of claim 1, wherein the two-dimensional material layer comprises a first two-dimensional material layer (540) and a second two-dimensional material layer (545). Regarding Claim 7 , Shin teaches the memory device of claim 6, wherein the first two-dimensional material layer and the second two-dimensional material layer comprise different materials (see above). Regarding Claim 9 , Shin teaches the memory device of claim 1, wherein the charge trap layer comprises silicon nitride, SiO2, HfO2, or TiO2 ([0082] SiN). Regarding Claim 11 , Shin teaches the memory device of claim 1, further comprising a tunneling barrier layer (120) between the charge trap layer and the channel layer. Regarding Claim 12 , Shin teaches the memory device of claim 1, further comprising a blocking insulating layer (graphene 545) between the two-dimensional material layer (2D material layer) and the gate electrode. Regarding Claim 13 , the explanation and citations are essentially the same as claim 1. Regarding Claim 16 , Shin teaches the memory device of claim 13, wherein the memory cell array extends in a direction perpendicular to the substrate (shown in Shin, Fig. 12). Regarding Claim 17 , the explanation and citations are essentially the same as claim 7. Regarding Claim 19 , the explanation and citations are essentially the same as claim 9 . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 2, 4-5, 8, 10, 14-15, 18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shin (US # 20230123234) in view of Huang (High-k Monolayer CaF2 as the Gate Dielectric for Two-Dimensional SiC-Based Field-Effect Transistors; ACS Applied Electronic Materials 2023 5 (9), 5082-5092; DOI: 10.1021/acsaelm.3c00829) . Regarding Claim 2 , although Shin discloses much of the claimed invention, it does not explicitly teach the memory device of claim 1, wherein the two-dimensional material layer comprises at least one of CaF2, NaF, MgF2, CdF2, MoS2, MoSe2, WS2, and WSe2. Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Huang is in the same or analogous field, and it teaches a memory device wherein a two-dimensional material layer comprises at least one of CaF2, NaF, MgF2, CdF2, MoS2, MoSe2, WS2, and WSe2 (see abstract teaching CaF 2 ). A person having ordinary skill in the art would have recognized that modifying the blocking insulation material of Shin with the 2D material suggested by Huang would be obvious. Specifically, the modification suggested by Huang would be to employ a memory device of claim 1, wherein the two-dimensional material layer comprises at least one of CaF2, NaF, MgF2, CdF2, MoS2, MoSe2, WS2, and WSe2. The rationale for this obvious modification is that CaF 2 provides superior leakage suppression, better electrostatic control, and minimal interface states and defects. Regarding Claim 4 , although Shin discloses much of the claimed invention, it does not explicitly teach the memory device of claim 1, wherein the two-dimensional material layer comprises a material with a band gap of 10 eV or more. Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Huang is in the same or analogous field, and it teaches using CaF 2 which has the band gap in the claimed range (approximately 11.8–12.1 eV). A person having ordinary skill in the art would have recognized that modifying the 2D material of Shin with the CaF 2 suggested by Huang would be obvious. Specifically, the modification suggested by Huang would be to employ a memory device of claim 1, wherein the two-dimensional material layer comprises a material with a band gap of 10 eV or more. The rationale for this obvious modification is that CaF 2 provides superior leakage suppression, better electrostatic control, and minimal interface states and defects. Regarding Claim 5 , although Shin discloses much of the claimed invention, it does not explicitly teach the memory device of claim 1, wherein a sum of a thickness of the two-dimensional material layer and a thickness of the charge trap layer is 10 nm or less. However, it is obvious for such a sum of thicknesses to be within that range because the 2D layer is less than 1 nm and the charge trap layers are typically within this range. It would have been obvious for a designer to try a sum of thicknesses as recited. It would accommodate the typical high-density integrations that are the driving force of all semiconductor memory devices. Regarding Claim 8 , Shin teaches the memory device of claim 1, wherein the charge trap layer comprises a material having a trap density of 1018/cm3 or more and 1020/cm3 or less ([0082] SiN has this material property in volume (bulk) trap density for memory applications). In the alternative, if this is not exact anticipation, then it at least would be obvious due to the typical use of a charge trapping material. Regarding Claim 10 , Shin teaches the memory device of claim 1, wherein the charge trap layer comprises a plurality of grain boundaries (the 2D material film is a van der Waals (vdW) surface and the natural result of forming non-vdW material, like SiN, on the vdW material is a plurality of grain boundaries). So this is a likely natural result of the materials system taught in the prior art, including the materials modifications teaching of Huang (CaF 2 ). Regarding Claim 14 , the explanation and citations are essentially the same as claim 2. Regarding Claim 15 , the explanation and citations are essentially the same as claim 4. Regarding Claim 18 , the explanation and citations are essentially the same as claim 8. Regarding Claim 20 , the explanation and citations are essentially the same as claim 10. Conclusion Certification of pertinent prior art: US 20220319602 A1 US 20240221832 A1 Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A JOHNSON whose telephone number is (571)272-9475. The examiner can normally be reached normally working Monday to Friday between 9 am and 6 pm Eastern Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A JOHNSON/Primary Examiner, Art Unit 2899 Application/Control Number: 18/581,186 Page 2 Art Unit: 2899 Application/Control Number: 18/581,186 Page 3 Art Unit: 2899 Application/Control Number: 18/581,186 Page 4 Art Unit: 2899 Application/Control Number: 18/581,186 Page 5 Art Unit: 2899 Application/Control Number: 18/581,186 Page 6 Art Unit: 2899 Application/Control Number: 18/581,186 Page 7 Art Unit: 2899 Application/Control Number: 18/581,186 Page 8 Art Unit: 2899
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