Prosecution Insights
Last updated: October 02, 2026
Application No. 18/581,496

QUANTUM DEVICE

Final Rejection §112
Filed
Feb 20, 2024
Priority
Feb 24, 2023 — JP 2023*027606
Examiner
PATERSON, BRIGITTE A
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NEC Corporation
OA Round
2 (Final)
76%
Grant Probability
Favorable
3-4
OA Rounds
1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
297 granted / 388 resolved
+8.5% vs TC avg
Strong +23% interview lift
Without
With
+22.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
21 currently pending
Career history
411
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
46.6%
+6.6% vs TC avg
§102
27.0%
-13.0% vs TC avg
§112
23.6%
-16.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 388 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1 and 2 recite “the first coupler and the second coupler respectively comprising inductive coupling ports and respectively having resonance frequencies variably controlled by applying a signal to the inductive coupling ports of the first coupler and the second coupler” (claim 1), “the first qubit and the second qubit respectively comprising inductive coupling ports and respectively having resonance frequencies variably controlled by applying a signal to the inductive coupling ports of the first qubit and the second qubit” (claim 1), “the third coupler and the third qubit respectively comprising inductive coupling ports and respectively having resonance frequencies variably controlled by applying a signal to the inductive coupling ports of the third coupler and the third qubit´(claim 1), “the fourth coupler comprising an inductive coupling port and having a resonance frequency variably controlled by applying a signal to the inductive coupling port of the fourth coupler” (claim 2), “the fourth qubit comprising an inductive coupling port and having a resonance frequency variably controlled by applying a signal to the inductive coupling port of the fourth qubit” (claim 2), “wherein the fifth coupler comprises an inductive coupling port and has a resonance frequency variably controlled by applying a signal to the inductive coupling port of the fifth coupler” (claim 2). The claims are indefinite because while claims 1 and 2 begin by reciting an apparatus, claims 1 and 2 further include a method of using the structure in applying a signal. The claim is not considered a product by process claim because the claim does not state that any feature was made using signal application. The claim recites that the apparatus is used in operation by applying a signal and inducing a resonant frequency. A single claim that includes both an apparatus and a method of using the apparatus is indefinite (See MPEP 2173.05(p)(II)). It is unclear if infringement would occur when the quantum device is created as an apparatus or when the quantum device is used in signal application to induce resonance. For the purposes of examination the process limitation will be treated as an intended result limitation (i.e. the apparatus must be capable of being used in applying a signal to the various qubits and couplers). Claims 3-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 3, 5, 7, 8 ,9 ,10 and 11 recite the following: Re claim 3, “wherein the inductive coupling port and the capacitive coupling port of each of the first to fourth qubits and the inductive coupling port and the capacitive coupling port of each of the first to fifth couplers provided on the wiring layer of the quantum chip” Re claim 5, “the capacitive coupling port of each of the qubits opposing one side edge in a longitudinal direction of the second arm electrode” Re claim 7, “the capacitive coupling port of each of the couplers includes a first end of a fourth line” Re claim 8, “a first wiring connecting via a corresponding bump to the capacitive coupling port of each qubit of the quantum chip… and a fourth wiring connecting via a corresponding bump to the capacitive coupling port of each coupler of the quantum chip” Re claim 9, “a plurality of first wirings, each connecting via a corresponding bump to the capacitive coupling port of each qubit of the quantum chip… and a plurality of fourth wirings, each connecting via a corresponding bump to the capacitive coupling port of each coupler of the quantum chip” Re claim 10, “the plurality of connectors connected via wiring to the terminals for external connection of the wiring substrate which are connected via the bumps to the capacitive coupling port of each of the first to fourth qubits and the first to fifth couplers of the quantum chip” Re claim 11, “wherein the PCB includes a plurality of first wirings, each connecting via the wiring substrate to the capacitive coupling port of each of the first to fourth qubits… and a plurality of fourth wirings, each connecting via the wiring substrate to the capacitive coupling port of each of the first to fifth couplers” There is no recitation in the preceding claims establishing antecedent basis for a capacitive port in the third and fourth qubits nor the third and fourth couplers. Therefore the claims are rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 recites “wherein the capacitive coupling port includes a first end of a second line, the second line having the first end opposed to one side edge in longitudinal direction of the second arm electrode, and a second end connected to a signal source.” It is unclear to which capacitive port the underlined portion of the claims is referring. The preceding claims establish a capacitive port in the first and second qubits and the first. Second, and fifth couplers. Therefore the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 8 recites “wherein the wiring substrate includes a wiring pattern in which one of the second wiring and the third wiring, each connecting to the capacitive coupling port and the wiring connecting to the inductive coupling port are arranged alternately.” It is unclear to which capacitive port and inductive coupling port the underlined portion of the claims is referring. Additionally the grammar of the underlined portion renders the claim indefinite because it is unclear if the wiring pattern includes a second wiring and a third wiring and what the “to which” phrase is referring. Additionally, it is unclear to which wiring “the wiring” is referring. The preceding claims establish a capacitive port in the first and second qubits and the first, second, and fifth couplers and an inductive port in the first, second, third and fourth qubits and the first, second, third, fourth and fifth couplers. Therefore the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Response to Arguments Applicant’s arguments with respect to claim(s) 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIGITTE A PATERSON whose telephone number is (571)272-1752. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at 571-272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BRIGITTE A. PATERSON Primary Examiner Art Unit 2896 /BRIGITTE A PATERSON/Primary Examiner, Art Unit 2896
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Prosecution Timeline

Feb 20, 2024
Application Filed
May 04, 2026
Non-Final Rejection mailed — §112
Aug 03, 2026
Response Filed
Aug 18, 2026
Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+22.6%)
2y 8m (~1m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 388 resolved cases by this examiner. Grant probability derived from career allowance rate.

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