Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 12/15/25 is acknowledged.
Claims 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/23/23.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Nishikawa et al. (USPGPub 20210142841) in view of Jang et al. (US PGPub 2014/0035026)
Claim 1: Nishikawa teaches a microelectronic device, comprising: a pair of stack structures (270), the pair comprising: a lower stack structure (290); and an upper stack structure (280) overlying the lower stack structure, the lower stack structure and the upper stack structure each comprising a vertically repeated sequence of material structures comprising insulative structures and conductive structures (281, 291); a source region (275) vertically interposed between the lower stack structure and the upper stack structure; a upper array of pillars extending, through the upper stack structure, from proximate the source region toward a first drain region (286) adjacent the upper stack structure; and a lower array of pillars extending, through the lower stack structure, from proximate the source region toward a second drain region (296) below the lower stack structure. Nishikawa does not teach at least some of the pillars of at least one of the upper array of pillars and the lower array of pillars, individually comprising channel material defining a Y-shaped base of a channel region. Jung teaches various shapes for the channel region to control the density of charge trap sites [0071] (Fig. 3A-C). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the channel of the pillars to comprise a Y-shape at its base to control the density of charge trap sites and is an obvious variant of the basic cylinder/pipe layout as taught by Jung [0071] (Fig. 3A-C).
Claim 4: Nishikawa teaches (see claim 1) a microelectronic device, comprising: a material structure between a lower drain region and an upper drain region, the material structure comprising: a lower deck comprising conductive structures and insulative structures arranged in tiers; an upper deck comprising additional conductive structures and additional insulative structures arranged in additional tiers; and an interdeck source region between the lower deck and the upper deck; slit structures extending through the material structure to divide the material structure into blocks (Fig. 1), the slit structures spacing the lower deck and the upper deck of one of the blocks from the lower deck and the upper deck of a neighboring one of the blocks; conductive bridge structures (SL0-SL2) [0007] (Fig. 1) extending across the slit structures from the interdeck source region of one of the blocks to the interdeck source region of the neighboring one of the blocks; and the blocks individually comprising pillar arrays comprising: a lower pillar array comprising pillars extending through the lower deck; and an upper pillar array comprising additional pillars extending through the upper deck. Nishikawa does not teach the pillars and the additional pillars having Y-shaped bases defined at least in part by a channel material. Jung teaches various shapes for the channel region to control the density of charge trap sites [0071] (Fig. 3A-C). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the channel of the pillars to comprise a Y-shape at its base to control the density of charge trap sites and is an obvious variant of the basic cylinder/pipe layout as taught by Jung [0071] (Fig. 3A-C).
Claim 5: Nishikawa teaches (see annotated figure 9B below) the interdeck source region (A) and the conductive bridge structures (275) comprise a substantially continuous region of at least one conductive material.
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Claim 9: Nishikawa teaches (ABS) (Fig. 2-3) [0049-0050] a stack of bit lines below the lower drain region.
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Nishikawa et al. (USPGPub 20210142841) in view of Jang et al. (US PGPub 2014/0035026), as applied to claim 1 above, and further in view of Nishida (US PGPub 2017/0062460).
Regarding claim 2, as described above, Nishikawa and Jang substantially read on the invention as claimed, except Nishikawa and Jang do not teach the at least some of the pillars individually comprise an insulative void laterally surrounded by the channel material. Nishida the at least some of the pillars individually comprise an insulative void laterally surrounded by the channel material.as air gaps are a known substitution for convention silicon oxide/ SiN commonly used in the dielectric core of a memory cell pillar [0021]. Therefore it would have been obvious to one of ordinary skill in the art at the time the invention was made to substitute one know element for another known element resulting in the predictable result of forming an insulative memory core (KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007)).
Claim 6: Nishida teaches (Fig. 1, 9) the slit structures comprise at least one dielectric material through which the conductive bridge structures horizontally extend. Insulative slit structures separating memory blocks is commonly known in the art as evidenced by Dai (US PGPub 2019/0096901).
Claim 7: Nishida teaches (Fig. 9) the interdeck source region defines tapering extensions along at least a lower elevation of the interdeck source region.
Claim 8: Nishida teaches the channel material substantially encloses an insulative void region.
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814
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