DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of Group I, species B, claims 1-10, 12 and 13, in the reply filed on 7/13/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 11 and 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/13/26.
Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Ishii, US Publication No. 20250212324 (e.g. See fig. 12 disclosing a glass substrate (10) with wiring layers formed above and below.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4 and 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suwadaishi, US Publication No. 20240312797 A1 in view of Bright et al., US Patent No. 6127726 A.
Suwadaishi teaches:
A printed circuit board, comprising (see figs. 11, 19 and 20):
a first substrate (90) unit including a plurality of build-up insulating layers (e.g. build-up insulating layers annotated) and a plurality of build-up wiring layers (e.g. wiring layers annotated) respectively disposed on or in the plurality of build-up insulating layers, each of the plurality of build-up wiring layers including circuits; and
a second substrate (1) unit including a glass layer (10), a first wiring layer (e.g. lower 21) and a second wiring layer (e.g. upper 22) disposed on a first surface (e.g. top surface) and a second surface (e.g. bottom surface) of the glass layer, respectively, an insulating layer (e.g. lower 22) disposed on the glass layer, and a third wiring layer (e.g. additional bottom layers 22; See para. [0067], [0072] disclosing “ The materials, the number of layers, and the like are not limited to the above, and may be appropriately set as necessary.”) disposed on the insulating layer, each of the first to third wiring layers including circuits,
wherein the second substrate unit (1) is stacked on the first substrate unit (90) or embedded in the first substrate unit,
wherein the first surface (e.g. top surface) of the glass layer opposes the second surface (e.g. bottom surface) of the glass layer, and… See Suwadaishi at para. [0001] – [0107].
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Suwadaishi is silent:
wherein an average pitch of the circuits of each of the first to third wiring layers is lower than an average pitch of the circuits of each of the plurality of build-up wiring layers.
Suwadaishi teaches the second substrate (1) is an interposer at para. [0099].
In an analogous art, Bright teaches: “A CSP includes the use of a substrate (interposer, or carrier, or substrate, or middle layer) to redistribute the pitch of peripheral array pads, which are normally very fine, as small as 0.075) to a larger pitch, such as 1.00 mm, 0.8 mm, 0.75 mm, and 0.5 mm on the printed circuit board.” See Bright at col 6, ln 1–17.
It would have been obvious to one of ordinary skill in the art to form in Suwadaishi “wherein an average pitch of the circuits of each of the first to third wiring layers is lower than an average pitch of the circuits of each of the plurality of build-up wiring layers” because Bright teaches interposers (-i.e. second substrate) redistribute a very fine, small pitch to a larger pitch in the printed circuit board (-i.e. first substrate)
Regarding claim 4:
Sawadaichi further teaches:
4. The printed circuit board according to claim 1, (see figs. 19-20 annotated above)
wherein the first substrate unit (90) further comprises a plurality of build-up via layers (e.g. via layers annotated in fig. 20), at least one of the plurality of build-up via layers penetrating through at least one of the plurality of build-up insulating layers,
the second substrate unit (10) further comprises a first via layer (11) penetrating through the glass layer (10) and connecting the first (e.g. lower 21) and second (e.g. upper 22) wiring layers, and a second via layer (32) penetrating through the insulating layer (e.g. lower 22) and connecting the first (e.g. lower 21) and third wiring layers (e.g. additional bottom layers 22 annotated in fig. 19),
each of the first (11) and second (32) via layers is tapered (e.g. taper up) in a direction opposite a tapering direction of the plurality of build-up via layers (e.g. taper down) as viewed in a cross-section of the printed circuit board, and
each of the plurality of build-up via layers, the first via layer, and the second via layer include a plurality of vias
Regarding claim 7:
Suwadaishi further teaches:
7. The printed circuit board according to claim 4, wherein the first and second wiring layers and the first via layer are in direct contact with the glass layer.
Regarding claim 8:
Suwadaishi further teaches:
8. The printed circuit board according to claim 1, wherein the glass layer includes plate glass, para. [0042], [0048].
Regarding claim 9:
Suwadaishi teaches the materials of the insulating layers at para. [0058].
Suwadaishi is silent regarding the material of the build-up insulating layers.
However, it would have been obvious to one having ordinary skill in the art to form “wherein each of the insulating layer and the plurality of build-up insulating layers includes Ajinomoto Build-up Film (ABF), Prepreg (PPG), or a Photoimageable dielectric (PID)”, since it is within the general skill of a worker in the art to select known material on the basis of its suitability for the intended purpose as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Regarding claim 10:
Suwadaishi further teaches:
10. The printed circuit board according to claim 1, further comprising: first and second semiconductor chips (e.g. see chips annotated in fig. 20) disposed on the second substrate unit (1) and interconnected to each other through the first to third wiring layers (e.g. see wiring layers annotated)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Suwadaishi with the teachings of Bright to enable the redistribution of a very fine, small pitch from the chip/interposer to a larger pitch in the printed circuit board. See Bright at col 6, ln 1–17.
Claim(s) 2, 3, 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suwadaishi in view of Bright, as applied to claim 1 above, in further view of Okawa, JP 2018010954 A (see attached English machine translation).
Regarding claim 2:
Suwadaishi teaches all the limitations of claim 1 above, but does not expressly teach:
wherein an average separation distance between adjacent layers among the first to third wiring layers is smaller than an average separation distance between adjacent layers among the plurality of build-up wiring layers.
In an analogous art, Okawa teaches:
2. The printed circuit board according to claim 1, (see figs. 2, 3 and 23) wherein an average separation distance between adjacent layers among the first to third wiring layers (e.g. of second substrate, interposer 200) is smaller than an average separation distance between adjacent layers among the plurality of build-up wiring layers (e.g. of first substrate, circuit substrate 9010, 10). See Okawa at pages 2-4 and 21.
Regarding claim 3:
One of ordinary skill in the art modifying Suwadaishi with Okawa to form the interposer (--i.e. second substrate) to be smaller than or embedded in the circuit substrate (-i.e. first substrate) as shown in Okawa’s figs. 2, 3 and 23 would arrive at the claimed limitation:
wherein a thickness of each of the glass layer and the insulating layer (e.g. of second substrate) is thinner than a thickness of each of the plurality of build-up insulating layers (e.g. of first substrate).
Regarding claim 12:
Okawa further teaches:
12. The printed circuit board according to claim 1, (see figs. 2 and 23) wherein the second substrate unit (200) is embedded in the first substrate unit (10), and a first outermost portion (e.g. top portion) of the second substrate unit is exposed from an outermost surface of an outermost build-up insulating layer among the plurality of build-up insulating layers (e.g. layers 1 to 7), and a side portion and a second outermost portion of the second substrate unit (200) are embedded in the plurality of build-up insulating layers (e.g. layers 1 to 7) to be covered with the plurality of build-up insulating layers. See Okawa at pages 2-4 and 21.
13. The printed circuit board according to claim 12, (see fig. 23) comprising a plurality of the second substrate units (200’, 200) embedded in the plurality of build-up insulating layers (e.g. layers 1 to 7). See Okawa at page 21.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Suwadaishi with the teachings of Okawa because “…the present embodiment includes the interposer substrate 200 in the recess 90...The distance of 10 can be reduced. Therefore, compared with the reference example 1, the heat dissipation efficiency from the electronic component 101 to the circuit board 10 can be increased.” See Okawa at page 6.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Suwadaishi in view of Bright, as applied to claim 1 above, in further view of Kikuchi et al. JP 2018110155 A.
Regarding claim 5:
Suwadaishi teaches all the limitations of claim 1 above and further teaches:
5. The printed circuit board according to claim 4, wherein at least one via among the plurality of vias in each of the plurality of build-up via layers, the first via layer, and the second via layer has a first end having a width wider than that of a second end opposing the first end, (e.g. In figs. 19-20 the vias are tapered up or tapered down.)
Suwadaishi is silent:
and as viewed in the cross-section of the printed circuit board a width of the first end of the at least one via of each of the first and second via layers is narrower than a width of the first end of the at least one via of each of the plurality of build-up via layers.
In an analogous art, Kikuchi teaches:
“The interposer substrate 10 has through-via wiring that penetrates the substrate, and converts the pitch of the fine connection terminals 23 of the semiconductor chip 20 into the pitch of the connection terminals of the circuit substrate 3.” See fig. 1, page 2.
It would have been obvious to one of ordinary skill in the art to form in Suwadaishi “and as viewed in the cross-section of the printed circuit board a width of the first end of the at least one via of each of the first and second via layers is narrower than a width of the first end of the at least one via of each of the plurality of build-up via layers” because Kikuchi teaches interposers (-i.e. second substrate) converts a fine pitch into a pitch of the circuit substrate (-i.e. first substrate)
Regarding claim 6:
Sawadaichi is silent:
wherein an average separation distance between adjacent vias among the plurality of vias in each of the first and second via layers is smaller than an average separation distance between adjacent vias among the plurality of vias in each of the plurality of build-up wiring layers.
Kikuchi teaches:
“The interposer substrate 10 has through-via wiring that penetrates the substrate, and converts the pitch of the fine connection terminals 23 of the semiconductor chip 20 into the pitch of the connection terminals of the circuit substrate 3.” See fig. 1, page 2.
It would have been obvious to one of ordinary skill in the art to form in Suwadaishi “wherein an average separation distance between adjacent vias among the plurality of vias in each of the first and second via layers is smaller than an average separation distance between adjacent vias among the plurality of vias in each of the plurality of build-up wiring layers” because Kikuchi teaches interposers (-i.e. second substrate) converts a fine pitch into a pitch of the circuit substrate (-i.e. first substrate)
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Suwadaishi with the teachings of Kikuchi to enable the redistribution of a fine pitch from the chip/interposer to a larger pitch in the circuit substrate. See Kikuchi at page 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
10 September 2026
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