Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Applicant’s amendment, filed 04/14/2026, has been received, entered into the record, respectfully and fully considered.
By this amendment, claims 1, 4, 8, 17, 19, and 20 have been amended. claims 2 and 3 are cancelled. Claim 21 is newly added. Thus, claims 1, 4-21 have been examined.
Any objection, claim interpretation and claim rejection not repeated below is withdrawn due to Applicant's amendments.
Response to Arguments
Applicant's arguments filed 04/14/2026 have been fully considered and have been addressed as follows. Applicant’s arguments include portions “a” and “b,” each being recited below and responded briefly.
a. Applicant argued on page 17-18 of the remarks:
Claim 1 and Claim 19
Applicant respectfully submits that the dummy rows 140 and 150 with their pass
transistors would not be considered as "test cells". However, even assuming arguendo that
the dummy rows 140 and 150 could be considered as "test cells" the pass transistors of
Beffa are configured to apply fixed voltages to the bitlines and therefore must remain
electrically connected to the voltage supply or ground. A transistor having a floating drain
would not perform the voltage-forcing function disclosed in Beffa. Instead, in Beffa, the transistors are either electrically coupled to bitline (BLx) or to power supply. This is intentional as Beffa are used to initialize test data by coupling fixed internal voltages directly to the bitlines. The configuration uses pass transistors (141-144 and 151-154) to connect bitlines to either the supply voltage or ground. The first dummy row (140), controlled by signal line DR1, applies the supply voltage to true bitlines and ground to complementary bitlines. Conversely, the second dummy row (150), controlled by DR2, provides the opposite (complementary) data pattern. During this process, the sense amplifiers are maintained in a disabled state, allowing these fixed potentials to establish a difference in potential that represents known test data before it is copied to other rows of the memory array.
In short, Beffa cannot have a floating drain transistor because its purpose is to force voltage onto the bitline.
In response to Applicant’s Argument “a,” Examiner would like to point out that Applicant’s arguments with respect to claim(s) 1 and 19 have been considered but are moot because the new referred reference Diep et al., US 10008271.
b. Applicant argued on page 22 of the remarks:
Claim 11
Applicant respectfully disagrees. Jo does not cure the deficiencies of Kajiya and Beffa. The cited portions of Jo (FIG. 7, 710, [0077], FIG. 6, [0073]-[0074]) describe measuring a single read current, through a selected memory cell, and during a read operation. It is not a test device.
In short Jo measures a single read current, in contrast to claim 11.
The Office Action does not provide any details how Jo discloses measuring a current provided to a power supply pad, let alone measuring a "first current", "second current", and a "third current" provided to a power supply pad. Instead, the methods of FIGS. 6 and 7 of Jo describe measuring one current, through a target memory cell, in response to a certain sequence of applied voltages. Further, the Office Action does not indicate what is, the alleged "test device" of Jo.
In response to Applicant’s Argument “b,” Examiner would like to point out that Jo, “a selector device” in Fig. 5 & Fig. 6 corresponds to “a test device”, Jo, [0031] states “A filamentary selector device can exhibit a first state (e.g., a first electrical resistance, or other suitable measurable characteristic) in the absence of a suitable external stimulus. The stimulus can have a threshold value or range of such values that induces the filamentary selector device to change from the first state to a second state while the stimulus is applied”, i.e., The stimulus here can be broadly interpreted as testing.
Further, Claim 11 recites “measure a first current provided to the power supply pad in response to activation of the first word line and the first bitline, a second current provided to the power supply pad in response to activation of the first dummy word line and the first bitline, and a third current provided to the power supply pad in response to activation of the first bitline.”, it is nothing more than measure a current by supply a voltage between activating wordline and bitline. Jo, Fig.7, [0077] recites “At 702, method 700 can comprise applying a disturb inhibition voltage to a non-target bitline of a 1TnR memory cell array. At 704, method 700 can comprise applying a second disturb inhibition voltage to a non-target wordline of the 1TnR memory cell array. In addition to the foregoing, at 706, method 700 can comprise applying an activation voltage across a target bitline and a target wordline of the 1TnR resistive memory cell array, where the target bitline and target wordline are respectively connected to a target memory cell.”
Accordingly, it would be obvious to one of ordinary skill in the art have arrived at the subject matter of claim 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KAJIYA et al., US 20250342895, hereinafter KAJIYA, in view of Beffa et al., US 6094734, hereinafter Beffa, in further view of Diep et al., US 10008271, hereinafter Diep., in further view of Diep et al., US 10008271, hereinafter Diep.
As per claim 1, KAJIYA teaches A memory device, comprising:
a first memory cell including a first electrical fuse and a first program transistor connected in series between a first bitline and a ground voltage node;
(Fig.1, FIG.2, [0057])
a second memory cell including a second electrical fuse and a second program transistor connected in series between the first bitline and the ground voltage node; and (Fig.1, FIG.2, [0057])
the first program transistor operates in response to a voltage level of a first word line,
the second program transistor operates in response to a voltage level of a second word line,
(KAJIYA, FIG.2, [0057])
EXCEPT
a first test cell including a first test transistor connected between the first bitline and the ground voltage node.
a second test cell including a second test transistor operating in response to a voltage level of a second dummy word line,
wherein:
the first test transistor operates in response to a voltage level of a first dummy word line,
the first bitline and a drain terminal of the first test transistor are electrically shorted to each other, and
a drain terminal of the second test transistor is electrically floating.
Beffa teaches
a first test cell including a first test transistor connected between the first bitline and the ground voltage node, and (Fig. 5, 140)
a second test cell including a second test transistor operating in response to a voltage level of a second dummy word line, (Fig.5, 9:24-55, the pass transistors 141-144 and 151-154)
wherein:
the first test transistor operates in response to a voltage level of a first dummy word line, (Fig.5, 9:24-35)
the first bitline and a drain terminal of the first test transistor are electrically shorted to each other, and (Fig.5, 9:24-55)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA to incorporate the teaching of the elements from Beffa as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
KAJIYA- Beffa teaches all elements as indicated above EXCEPT
a drain terminal of the second test transistor is electrically floating.
Diep teaches
a drain terminal of the second test transistor is electrically floating. (Diep, Fig.16, 23:60-24:12, ......This step also includes floating the drain-end select gate transistor at a first drain-end select gate transistor voltage while a voltage of the dummy memory cell is driven at a first dummy memory cell voltage.)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA- Beffa to incorporate the teaching of the elements from Diep as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 19, KAJIYA teaches A memory device, comprising:
a memory cell array including a plurality of memory cells connected to a first bitline; (Fig.1, FIG.2, [0057]) and
EXCEPT
a test cell array including a first test cell and a second test cell connected to the first bitline,
wherein the first test cell comprises:
a first test transistor including a first drain terminal electrically connected to the first bitline, and a first source terminal connected to a ground voltage node,
wherein the second test cell comprises:
a second test transistor including a second drain terminal not electrically connected to the first bitline, and a second source terminal connected to the ground voltage node.
Beffa teaches
a test cell array (FIG.5, two dummy rows 140 and 150) including a first test cell and a second test cell connected to the first bitline, (FIG.5, 140 and 150)
wherein the first test cell comprises:
a first test transistor including a first drain terminal electrically connected to the first bitline, and a first source terminal connected to a ground voltage node,
wherein the second test cell comprises:
a second test transistor including a second drain terminal
(Fig.5, 9:24-55, the pass transistors 141-144 and 151-154)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA to incorporate the teaching of the elements from Beffa as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
KAJIYA- Beffa teaches all elements as indicated above EXCEPT
a second test transistor including a second drain terminal that is electrically floating,
Diep teaches
a second test transistor including a second drain terminal that is electrically floating, (Diep, Fig.16, 23:60-24:12, ......This step also includes floating the drain-end select gate transistor at a first drain-end select gate transistor voltage while a voltage of the dummy memory cell is driven at a first dummy memory cell voltage.)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA- Beffa to incorporate the teaching of the elements from Diep as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 4, KAJIYA- Beffa-Diep teaches The memory device applied above in claim 1, Beffa further teaches wherein:
the first bitline and a drain terminal of the second test transistor are electrically isolated from each other. (Fig.5, 9:24-55)
As per claim 20, KAJIYA- Beffa-Diep teaches The memory device applied above in claim 19, Beffa further teaches wherein:
the first test cell comprises:
a first bitline contact connected to the first bitline;
a first drain contact connected to the first drain terminal; and
a first conductor connected to the first bitline contact and the first drain contact through one or more vias, and
(Fig. 5, 140)
the second test cell comprises:
a second bitline contact connected to the first bitline;
a second drain contact connected to the second drain terminal;
a second conductor; and
an interlayer insulating layer electrically separating the second conductor, the second bitline contact, and the second drain contact.
(Fig.5, 9:24-55)
Claim(s) 5-7, and 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over KAJIYA et al., US 20250342895, hereinafter KAJIYA, in view of Beffa et al., US 6094734, hereinafter Beffa, in further view of Diep et al., US 10008271, hereinafter Diep., in further view of Jo et al., US 20160005461, hereinafter Jo.
As per claim 5, KAJIYA- Beffa-Diep teaches The memory device applied above in claim 4, EXCEPT configured to perform testing wherein:
the first word line is activated at a first time point,
the first dummy word line is activated at a second time point, and
the second dummy word line is activated at a third time point.
Jo teaches
the first word line is activated at a first time point,
the first dummy word line is activated at a second time point, and
the second dummy word line is activated at a third time point.
(FIG. 7, 710, [0077], FIG. 6, [0073]-[0074])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA- Beffa-Diep to incorporate the teaching of the elements from Jo as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 6, KAJIYA- Beffa-Diep-Jo teaches the memory device applied above in claim 5, Jo further teaches wherein during testing:
at the first time point, the first and second dummy word lines and the second word line are deactivated,
at the second time point, the first and second word lines and the second dummy word line are deactivated,
at the third time point, the first and second word lines and the first dummy word line are deactivated.
(FIG. 7, 710, [0077], FIG. 6, [0073]-[0074])
As per claim 7, KAJIYA- Beffa-Diep-Jo teaches the memory device applied above in claim 6, Jo teaches further comprising:
a power supply rail connected to a power supply pad; (FIG.5, DVC2, 26; 8:43 Vcc supply rail) and
KAJIYA further teaches
a first bitline select switch connected between the power supply rail and the first bitline, wherein during testing the first bitline select switch is turned on at the first time point, the second time point, and the third time point.
(FIG.2, [0057] the blow transistor TR2 is an example of a selection element and corresponds to a selection transistor.)
As per claim 11, KAJIYA teaches A test system, comprising:
a memory device including a first memory cell connected to a first word line and a first bitline, (Fig.1, FIG.2, [0057])
EXCEPT
a first test cell connected to a first dummy word line and the first bitline, and a power supply pad connected to the first bitline; and
Beffa teaches
a first test cell connected to a first dummy word line and the first bitline (Fig. 5, 140) , and a power supply pad connected to the first bitline (FIG.5, DVC2, 26); and
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA to incorporate the teaching of the elements from Beffa as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
KAJIYA-Beffa teaches all elements as applied above EXCEPT
a test device configured to measure a first current provided to the power supply pad in response to activation of the first word line and the first bitline, a second current provided to the power supply pad in response to activation of the first dummy word line and the first bitline, and a third current provided to the power supply pad in response to activation of the first bitline.
Jo teaches
a test device configured to measure
a first current provided to the power supply pad in response to activation of the first word line and the first bitline,
a second current provided to the power supply pad in response to activation of the first dummy word line and the first bitline, and
a third current provided to the power supply pad in response to activation of the first bitline.
(FIG. 7, 710, [0077], FIG. 6, [0073]-[0074])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA-Beffa to incorporate the teaching of the elements from Jo as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 12, KAJIYA- Beffa-Jo teaches The test system applied above in claim 11, KAJIYA further teaches wherein:
the first memory cell comprises a first program transistor and a first electrical fuse connected in series between the first bitline and a ground voltage, and …
wherein the first program transistor operates in response to a voltage level of the first word line, and
(Fig.1, FIG.2, [0057])
Beffa further teaches
the first test cell comprises a first test transistor connected between the first bitline and the ground voltage, (Fig. 5, 140)
the first test transistor operates in response to a voltage level of the first dummy word line.
(Fig. 5, 9:24-35, the memory array includes two dummy rows 140 and 150…...)
As per claim 13, KAJIYA- Beffa-Jo teaches The test system applied above in claim 12, Beffa further teaches wherein the test device further comprises a second test cell connected to the first bitline and a second dummy word line. (Fig.5, 9:24-55, the pass transistors 141-144 and 151-154)
As per claim 14, KAJIYA- Beffa-Jo teaches The test system applied above in claim 13, Beffa further teaches wherein the second test cell comprises:
a second test transistor including a gate terminal connected to the second dummy word line, a source terminal connected to the ground voltage, and a drain terminal not electrically connected to the first bitline. (Fig.5, 9:24-55)
Claim(s) 8-9, 15-16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over KAJIYA et al., US 20250342895, hereinafter KAJIYA, in view of Beffa et al., US 6094734, hereinafter Beffa, in further view of Diep et al., US 10008271, hereinafter Diep., in further view of Jo et al., US 20160005461, hereinafter Jo, in further view of KIM, US 20220328085, hereinafter KIM.
As per claim 8, KAJIYA- Beffa-Diep-Jo teaches the memory device of claim 7, EXCEPT wherein during the testing, a resistance value of the first electrical fuse is measured based on:
a first current provided to the power supply pad from an external device at the first time point;
a second current provided to the power supply pad from the external device at the second time point; and
a third current provided to the power supply pad from the external device at the third time point.
Kim teaches
wherein during the testing, the resistance value of the first electrical fuse is measured based on:
a first current provided to the power supply pad from an external device at the first time point;
a second current provided to the power supply pad from the external device at the second time point; and
a third current provided to the power supply pad from the external device at the third time point.
([0074]-[0076] the test device may store the measured reference resistance value and a value of a read current corresponding thereto in or within the memory device, e.g. store the read current in a fuse array and/or an anti-fuse array. After the memory device is used by the end user, an improved (e.g. optimal) read current value stored in the memory device may be used in the normal read operation. [0073])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA-Beffa-Jo to incorporate the teaching of the elements from Kim as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 9, KAJIYA- Beffa-Diep-Jo teaches the memory device of claim 7, Beffa further teaches therein the first bitline select switch comprises:
a N-channel metal-oxide semiconductor (NMOS) transistor connected between the first bitline and the power supply rail, and turned on at the first time point, the second time point, and the third time point. (6:23-29, n-channel field effect transistor 78)
As per claim 15, KAJIYA- Beffa-Jo teaches The test system of claim 12, EXCEPT wherein the test device is configured to calculate a resistance value of the first electrical fuse based on the first to third currents.
Kim teaches wherein the test device is configured to calculate a resistance value of the first electrical fuse based on the first to third currents. ([0074]-[0076])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA-Beffa-Jo to incorporate the teaching of the elements from Kim as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 16, KAJIYA- Beffa-Jo-Kim teaches The test system of claim 15, Kim further teaches wherein the test device is configured to provide a first voltage to the power supply pad while measuring the first, second, and third currents.
([0074]-[0076])
As per claim 18, KAJIYA- Beffa-Jo teaches The test system of claim 12, EXCEPT wherein sizes of the first program transistor and the first test transistor correspond to each other.
Kim teaches wherein sizes of the first program transistor and the first test transistor correspond to each other. ([0074]-[0076])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA-Beffa-Jo to incorporate the teaching of the elements from Kim as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
Claim(s) 10 and Claim 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over KAJIYA et al., US 20250342895, hereinafter KAJIYA, in view of Beffa et al., US 6094734, hereinafter Beffa, in further view of Diep et al., US 10008271, hereinafter Diep., in further view of KIM, US 20220328085, hereinafter KIM.
As per claim 10, KAJIYA- Beffa-Diep teaches The memory device of claim 1,
EXCEPT wherein: a size of the first test transistor corresponds to a size of the first program transistor.
Kim teaches wherein: a size of the first test transistor corresponds to a size of the first program transistor. ([0074]-[0076])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA-Beffa to incorporate the teaching of the elements from Kim as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 21, KAJIYA- Beffa-Diep teaches The memory device of claim 19,
EXCEPT wherein:
each of the plurality of memory cells includes a program transistor,
wherein the first test transistor has the same size of each of the first program transistors.
Kim teaches wherein:
each of the plurality of memory cells includes a program transistor,
wherein the first test transistor has the same size of each of the first program transistors.
([0074]-[0076])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA-Beffa to incorporate the teaching of the elements from Kim as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
Examiner’s Notes
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fifield et al., US 8027207, Leakage Compensated Reference Voltage Generation System
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/RONG TANG/ Examiner, Art Unit 2111
/MARK D FEATHERSTONE/ Supervisory Patent Examiner, Art Unit 2111
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