Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/20/2024 is being considered by the examiner.
Claim Objections
Claim 17 is objected to because of the following informalities:
Claim 17 line 4 from bottom recites “resistance value”, it should be “the resistance value”.
Any claim not specifically mentioned above, is objected due to its dependency on the objected claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 line 1 recites the limitation “the resistance value". There is insufficient antecedent basis for this limitation in the claim.
Claims 11-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
In order for “a third current provided to the power supply pad in response to activation of the first bitline” as claimed in Claim 11, a wordline activation will be needed.
Any claim not specifically mentioned above, is rejected due to its dependency on the rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KAJIYA et al., US 20250342895, hereinafter KAJIYA, in view of Beffa et al., US 6094734, hereinafter Beffa.
As per claim 1, KAJIYA teaches A memory device, comprising:
a first memory cell including a first electrical fuse and a first program transistor connected in series between a first bitline and a ground voltage node;
(Fig.1, FIG.2, [0057])
a second memory cell including a second electrical fuse and a second program transistor connected in series between the first bitline and the ground voltage node; and (Fig.1, FIG.2, [0057])
EXCEPT
a first test cell including a first test transistor connected between the first bitline and the ground voltage node.
Beffa teaches
a first test cell including a first test transistor connected between the first bitline and the ground voltage node. (Fig. 5, 140)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA to incorporate the teaching of the elements from Beffa as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 19, KAJIYA teaches A memory device, comprising:
a memory cell array including a plurality of memory cells connected to a first bitline; (Fig.1, FIG.2, [0057]) and
EXCEPT
a test cell array including a first test cell and a second test cell connected to the first bitline,
wherein the first test cell comprises:
a first test transistor including a first drain terminal electrically connected to the first bitline, and a first source terminal connected to a ground voltage node,
wherein the second test cell comprises:
a second test transistor including a second drain terminal not electrically connected to the first bitline, and a second source terminal connected to the ground voltage node.
Beffa teaches
a test cell array (FIG.5, two dummy rows 140 and 150) including a first test cell and a second test cell connected to the first bitline, (FIG.5, 140 and 150)
wherein the first test cell comprises:
a first test transistor including a first drain terminal electrically connected to the first bitline, and a first source terminal connected to a ground voltage node,
wherein the second test cell comprises:
a second test transistor including a second drain terminal not electrically connected to the first bitline, and a second source terminal connected to the ground voltage node.
(Fig.5, 9:24-55, the pass transistors 141-144 and 151-154)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA to incorporate the teaching of the elements from Beffa as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 2, KAJIYA- Beffa teaches the memory device applied above in claim 1, KAJIYA further teaches wherein:
the first program transistor operates in response to a voltage level of a first word line,
the second program transistor operates in response to a voltage level of a second word line, and (FIG.2, [0057])
Beffa further teaches
the first test transistor operates in response to a voltage level of a first dummy word line. (Fig.5, 9:24-35)
As per claim 3, KAJIYA- Beffa teaches the memory device applied above in claim 2, Beffa teaches further comprising:
a second test cell including a second test transistor operating in response to a voltage level of a second dummy word line. (Fig.5, 9:24-55, the pass transistors 141-144 and 151-154)
As per claim 4, KAJIYA- Beffa teaches the memory device applied above in claim 3, Beffa further teaches wherein:
the first bitline and a drain terminal of the first test transistor are electrically shorted to each other,
the first bitline and a drain terminal of the second test transistor are electrically isolated from each other.
(Fig.5, 9:24-55)
As per claim 20, KAJIYA- Beffa teaches the memory device applied above in claim 19, Beffa further teaches wherein:
the first test cell comprises:
a first bitline contact connected to the first bitline;
a first drain contact connected to the first drain terminal; and
a first conductor connected to the first bitline and the first drain contact through one or more vias, and
(Fig. 5, 140)
the second test cell comprises:
a second bitline contact connected to the first bitline;
a second drain contact connected to the second drain terminal;
a second conductor; and
an interlayer insulating layer electrically separating the second conductor, the second bitline contact, and the second drain contact.
(Fig.5, 9:24-55)
Claim(s) 5-7, and 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over KAJIYA et al., US 20250342895, hereinafter KAJIYA, in view of Beffa et al., US 6094734, hereinafter Beffa, in further view of Jo et al., US 20160005461, hereinafter Jo.
As per claim 5, KAJIYA- Beffa teaches the memory device applied above in claim 4, EXCEPT configured to perform testing wherein:
the first word line is activated at a first time point,
the first dummy word line is activated at a second time point, and
the second dummy word line is activated at a third time point.
Jo teaches
the first word line is activated at a first time point,
the first dummy word line is activated at a second time point, and
the second dummy word line is activated at a third time point.
(FIG. 7, 710, [0077], FIG. 6, [0073]-[0074])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA- Beffa to incorporate the teaching of the elements from Jo as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 6, KAJIYA- Beffa-Jo teaches the memory device applied above in claim 5, Jo further teaches wherein during testing:
at the first time point, the first and second dummy word lines and the second word line are deactivated,
at the second time point, the first and second word lines and the second dummy word line are deactivated,
at the third time point, the first and second word lines and the first dummy word line are deactivated.
(FIG. 7, 710, [0077], FIG. 6, [0073]-[0074])
As per claim 7, KAJIYA- Beffa-Jo teaches the memory device applied above in claim 6, Jo teaches further comprising:
a power supply rail connected to a power supply pad; (FIG.5, DVC2, 26; 8:43 Vcc supply rail) and
KAJIYA further teaches
a first bitline select switch connected between the power supply rail and the first bitline, wherein during testing the first bitline select switch is turned on at the first time point, the second time point, and the third time point.
(FIG.2, [0057] the blow transistor TR2 is an example of a selection element and corresponds to a selection transistor.)
As per claim 11, KAJIYA teaches A test system, comprising:
a memory device including a first memory cell connected to a first word line and a first bitline, (Fig.1, FIG.2, [0057])
EXCEPT
a first test cell connected to a first dummy word line and the first bitline, and a power supply pad connected to the first bitline; and
Beffa teaches
a first test cell connected to a first dummy word line and the first bitline (Fig. 5, 140) , and a power supply pad connected to the first bitline (FIG.5, DVC2, 26); and
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA to incorporate the teaching of the elements from Beffa as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
KAJIYA-Beffa teaches all elements as applied above EXCEPT
a test device configured to measure a first current provided to the power supply pad in response to activation of the first word line and the first bitline, a second current provided to the power supply pad in response to activation of the first dummy word line and the first bitline, and a third current provided to the power supply pad in response to activation of the first bitline.
Jo teaches
a test device configured to measure a first current provided to the power supply pad in response to activation of the first word line and the first bitline, a second current provided to the power supply pad in response to activation of the first dummy word line and the first bitline, and a third current provided to the power supply pad in response to activation of the first bitline.
(FIG. 7, 710, [0077], FIG. 6, [0073]-[0074])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA-Beffa to incorporate the teaching of the elements from Jo as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 12, KAJIYA- Beffa-Jo teaches The test system applied above in claim 11, KAJIYA further teaches wherein:
the first memory cell comprises a first program transistor and a first electrical fuse connected in series between the first bitline and a ground voltage, and …
wherein the first program transistor operates in response to a voltage level of the first word line, and
(Fig.1, FIG.2, [0057])
Beffa further teaches
the first test cell comprises a first test transistor connected between the first bitline and the ground voltage, (Fig. 5, 140)
the first test transistor operates in response to a voltage level of the first dummy word line.
(Fig. 5, 9:24-35, the memory array includes two dummy rows 140 and 150…...)
As per claim 13, KAJIYA- Beffa-Jo teaches The test system applied above in claim 12, Beffa further teaches wherein the test device further comprises a second test cell connected to the first bitline and a second dummy word line. (Fig.5, 9:24-55, the pass transistors 141-144 and 151-154)
As per claim 14, KAJIYA- Beffa-Jo teaches The test system applied above in claim 13, Beffa further teaches wherein the second test cell comprises:
a second test transistor including a gate terminal connected to the second dummy word line, a source terminal connected to the ground voltage, and a drain terminal not electrically connected to the first bitline. (Fig.5, 9:24-55)
Claim(s) 8-9, 15-16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over KAJIYA et al., US 20250342895, hereinafter KAJIYA, in view of Beffa et al., US 6094734, hereinafter Beffa, in further view of Jo et al., US 20160005461, hereinafter Jo, in further view of KIM, US 20220328085, hereinafter KIM.
As per claim 8, KAJIYA- Beffa-Jo teaches The memory device of claim 7, EXCEPT wherein during the testing, the resistance value of the first electrical fuse is measured based on:
a first current provided to the power supply pad from an external device at the first time point;
a second current provided to the power supply pad from the external device at the second time point; and
a third current provided to the power supply pad from the external device at the third time point.
Kim teaches
wherein during the testing, the resistance value of the first electrical fuse is measured based on:
a first current provided to the power supply pad from an external device at the first time point;
a second current provided to the power supply pad from the external device at the second time point; and
a third current provided to the power supply pad from the external device at the third time point.
([0074]-[0076] the test device may store the measured reference resistance value and a value of a read current corresponding thereto in or within the memory device, e.g. store the read current in a fuse array and/or an anti-fuse array. After the memory device is used by the end user, an improved (e.g. optimal) read current value stored in the memory device may be used in the normal read operation. [0073])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA-Beffa-Jo to incorporate the teaching of the elements from Kim as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 9, KAJIYA- Beffa-Jo teaches The memory device of claim 7, Beffa further teaches therein the first bitline select switch comprises:
a N-channel metal-oxide semiconductor (NMOS) transistor connected between the first bitline and the power supply rail, and turned on at the first time point, the second time point, and the third time point. (6:23-29, n-channel field effect transistor 78)
As per claim 15, KAJIYA- Beffa-Jo teaches The test system of claim 12, EXCEPT wherein the test device is configured to calculate a resistance value of the first electrical fuse based on the first to third currents.
Kim teaches wherein the test device is configured to calculate a resistance value of the first electrical fuse based on the first to third currents. ([0074]-[0076])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA-Beffa-Jo to incorporate the teaching of the elements from Kim as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
As per claim 16, KAJIYA- Beffa-Jo-Kim teaches The test system of claim 15, Kim further teaches wherein the test device is configured to provide a first voltage to the power supply pad while measuring the first, second, and third currents.
([0074]-[0076])
As per claim 18, KAJIYA- Beffa-Jo teaches The test system of claim 12, EXCEPT wherein sizes of the first program transistor and the first test transistor correspond to each other.
Kim teaches wherein the test device is configured to provide a first voltage to the power supply pad while measuring the first, second, and third currents.
([0074]-[0076])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA-Beffa-Jo to incorporate the teaching of the elements from Kim as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over KAJIYA et al., US 20250342895, hereinafter KAJIYA, in view of Beffa et al., US 6094734, hereinafter Beffa, in further view of KIM, US 20220328085, hereinafter KIM.
As per claim 10, KAJIYA- Beffa-Jo teaches The memory device of claim 1,
EXCEPT wherein: a size of the first test transistor corresponds to a size of the first program transistor.
Kim teaches wherein: a size of the first test transistor corresponds to a size of the first program transistor. ([0074]-[0076])
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to have modified KAJIYA-Beffa-Jo to incorporate the teaching of the elements from Kim as indicated above, in order to determining the memory device is functioning properly. (Beffa ,1:18)
Examiner’s Notes
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fifield et al., US 8027207, Leakage Compensated Reference Voltage Generation System
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/RONG TANG/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111