Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, identified as encompassing Claims 1-20 in Figures 2A-11 is acknowledged. No further arguments or elections have been made, and therefore the resection is maintained and made final.
Note by the Examiner
For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 9-12, 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0216340 A1), hereinafter as L1, and Chang et al. (US 2022/0406621 A1), hereinafter as C1.
Regarding Claim 1, L1 discloses a method (see FIGs. 1-20 [0005-0006] ln. 1 “FIG. 1 illustrates a flow chart of a method for forming a semiconductor device…FIGS. 2-20 illustrate fragmentary cross-sectional views of a workpiece undergoing various fabrication processes in the method of FIG. 1) comprising:
forming a first de-bond structure ([0015] ln. 3 “the stack 204 includes a plurality of channel layers 208 interleaved by a plurality of sacrificial layers 206” where these elements make up a de-bond structure) over a first substrate (see FIG. 2, element 202, and [0014] ln. 2 “the workpiece 200 may include a substrate 202” where the elements 206 and 208 are over the substrate 202), wherein forming the first de-bond structure comprises:
depositing a first de-bond layer (see FIG. 2, element 206, [0015] ln. 3 “sacrificial layers 206”) over the first substrate (see FIG. 2 where element 206 is formed over the substrate 202);
depositing a first silicon layer over (see FIG. 2, element 208, and [0015] ln. 5 “the channel layers 208 are formed of silicon (Si)”) the first de-bond layer (see FIG. 2 where the silicon layer 208 is disposed over the sacrificial layer 206);
depositing a second de-bond layer over the first silicon layer (a second layer 206 is disposed over 208; and
depositing a second silicon layer over the second de-bond layer (see FIG. 2, elements 206 and 208, and [0015] “the stack 204 includes a plurality of channel layers 208 interleaved by a plurality of sacrificial layers 206” where this alternating fashion of silicon layer 208 and sacrificial layer 206 make up the first and second layers of each type within the stack portion 204B);
epitaxially growing a first multi-layer stack (see FIG. 2, element 204T, [0016] ln. 13 “the stack 204 may be vertically divided into…top portion 204T”, where the layers included in this portion make up the first multi-layer stack) over the first de-bond structure (see FIG. 2 where the stack 204T is formed over the substrate 202);
bonding the first multi-layer stack (element 204T) to a second multi-layer stack (see FIG., 2 element 204M, [0016] ln. 14 “a middle portion 204M”); and
L1 does not explicitly disclose performing a first laser annealing process to ablate the first silicon layer and portions of the first de-bond layer and the second de-bond layer in order to de-bond the first substrate from the first multi-layer stack.
C1 discloses performing a first laser annealing process (see FIGs. 4 and 5, element 68, [0044] ln . 5 “laser beam 68” and [0050] for a description of the removal process) to ablate the first silicon layer (see FIGs. 4 and 5, element 22, [0018] ln. 1 “layer 22… layer 22 is formed of a material that is transparent to the laser beam used in a subsequent de-bonding process… layer 22 is formed of or comprises an oxide-based material, which may be silicon oxide”) and portions of the first de-bond layer (see FIGs. 4 and 5, element 24, [0019] ln. 1 “absorption layer 24”) and the second de-bond layer (see FIGs. 4 and 5, element 26, [0026] ln. 1 “pad layer 26”) in order to de-bond the first substrate (see FIGs. 4 and 5, element 20, and [0018] ln. 2 “base carrier 20”) from the first multi-layer stack (see FIGs. 4 and 5, where the base carrier 20 is removed from the multi-layer stack made by elements 22, 24, and 26, through the process of laser removal 68).
The laser removal process as disclosed in C1 is incorporated into the method process of L1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of C1 into L1 as this is the use of a known technique to improve the removal process of layers within a device and therefore yields predictable results. The process of laser annealing provides a precise and efficient way of removing layers withing devices and is favorable process to not harm the internal structure of the device while still removing layers. The use of a known technique to improve a device yields predictable results (see C1 [0015] and [0017]).
Regarding Claim 2, L1 and C1 disclose the method of claim 1 further where L1 further discloses comprising:
patterning the second silicon layer, the first multi-layer stack, and the second multi-layer stack to form a fin (see FIG. 4, element 210, and [0018] ln. 3 “the stack 204 and a portion of the substrate 202 are patterned to form the fin-shaped structure 210”) , the fin comprising a plurality of lower nanostructures (see FIG. 5, element 204B, which now marks the nanostructure created by the patterning of the fin by elements 206 and 208) alternatingly stacked with first dummy nanostructures (elements 206 and 208 are alternately stacked within the stack 204B) and a plurality of upper nanostructures over the plurality of lower nanostructures (see FIG. 5, elements 204T and 204M, [0016] ln. 14 “middle portion 204M over the bottom portion 204B, and a top portion 204T), the plurality of upper nanostructures being alternatingly stacked with second dummy nanostructures (elements 206 and 208 are alternately stacked within the stack 204M and 204T).
Regarding Claim 3, L1 and C1 disclose the method of claim 2 further comprising:
replacing the first dummy nanostructures with a first gate stack (see FIG. 14, element 260, [0035] ln. 2 “gate structure 260”), the first gate stack surrounding each of the plurality of lower nanostructures (see FIG. 14, where the gate structures are in the lower portions of the fins 210, surrounding elements 206 and 208); and
replacing the second dummy nanostructures with a second gate stack (see FIG. 14 where the top nanostructure is also replaced by a gate structure 260), the second gate stack surrounding each of the plurality of upper nanostructures (see FIG. 14, where the gate structures are in the lower portions of the fins 210, surrounding elements 206 and 208).
Regarding Claim 4, L1 and C1 disclose the method of claim 1, wherein C1 further discloses performing the first laser annealing process (element 68) comprises scanning a laser beam that is emitted by a laser over a top surface of the first substrate (see FIG. 4, where the laser element 68 scans through the substrate 20, also see [0044] ln. 7 “laser beam 68 has a wavelength that allows it to penetrate through base carrier 20”), wherein the laser operates in an infrared region with a wavelength that is in a range from 500 to 2500 nm (see [0020] ln. 10 “using an Infrared (IR) laser having wavelengths in the range between about 1,800 nm and about 2,200 nm” which is in the presented range).
Regarding Claim 9, L1 and C1 disclose the method of claim 1, wherein where L1 further discloses each of the first de-bond layer and the second de-bond layer comprises germanium, silicon germanium (see [0015] ln. 6 “sacrificial layers 206 are formed of silicon germanium (SiGe)”).
Regarding Claim 10, L1 discloses a method (see FIGs. 1-20 [0005-0006] ln. 1 “FIG. 1 illustrates a flow chart of a method for forming a semiconductor device…FIGS. 2-20 illustrate fragmentary cross-sectional views of a workpiece undergoing various fabrication processes in the method of FIG. 1) comprising:
depositing a first de-bond layer (see FIG. 3, element 206, [0015] ln. 3 “sacrificial layers 206”) over a first substrate (see FIG. 3, element 202, and [0014] ln. 2 “the workpiece 200 may include a substrate 202” where the element 206 is over the substrate);
depositing a first silicon layer (see FIG. 3, element 208, and [0015] ln. 5 “the channel layers 208 are formed of silicon (Si)”) over the first de-bond layer;
depositing a second de-bond layer (see the second element 206, and attached figure below this claim) over the first silicon layer;
depositing a second silicon layer (see the second element 208, and attached figure below this claim) over the second de-bond layer ;
epitaxially growing a first semiconductor layer and a second semiconductor layer over the second silicon layer (Elements 206 and 208 are made of semiconducting materials, see [0022] ln. 9 “the channel layers 208 consist essentially of silicon (Si) and sacrificial layers 206 consist essentially of silicon germanium (SiGe)” and are able to serve the purpose of semiconducting layers. See attached figure below this claim for representation of first and second semiconductor layers);
epitaxially growing a third semiconductor layer and a fourth semiconductor layer (See attached figure below this claim for representation of third and fourth semiconductor layers)
L1 does not disclose over a second substrate;
L1 discloses depositing a first bonding layer over the second semiconductor layer;
depositing a second bonding layer over the fourth semiconductor layer;
bonding the first bonding layer to the second bonding layer to form a bonded layer (See attached figure below this claim for representation); and
after bonding the first bonding layer to the second bonding layer (See the attached figure where the two layers are bonded),
L1 does not disclose ablating the first de-bond layer, the first silicon layer, and the second de-bond layer using a laser anneal process to de-bond the first substrate from the second silicon layer, the first semiconductor layer, and the second semiconductor layer.
C1 discloses over a second substrate (see FIGs. 4 and 5, element 20, 60, and 64, [0018] ln. 2 “base carrier 20”, which represents the first substrate and [0042] ln. 3 “base carrier 64” which represents the second. Where a wafer structure 60, is disposed between the two substrates, see [0034] “device wafer 60”).
C1 discloses ablating the first de-bond layer (see FIGs. 4 and 5, element 24, [0019] ln. 1 “absorption layer 24”), the first silicon layer (see FIGs. 4 and 5, element 22, [0018] ln. 1 “layer 22… layer 22 is formed of a material that is transparent to the laser beam used in a subsequent de-bonding process… layer 22 is formed of or comprises an oxide-based material, which may be silicon oxide”), and the second de-bond layer (see FIGs. 4 and 5, element 26, [0026] ln. 1 “pad layer 26”) using a laser anneal process (see FIGs. 4 and 5, element 68, [0044] ln . 5 “laser beam 68” and [0050] for a description of the removal process) to de-bond the first substrate (element 20) from the second silicon layer (see FIGs. 4 and 5, element 26, [0026] ln. 1 “pad layer 26…pad layer 26 is formed of or comprises a silicon-based material”), the first semiconductor layer (see FIGs. 4 and 5, element 30, and [00031] ln. 1 “bond layer 30….is formed of or comprises a silicon-containing dielectric material”, and the second semiconductor layer (see FIGs. 4 and 5, element 34, and [0034] ln. 6 “bond layer 34”).
The laser removal process of one substrate as disclosed in C1 is incorporated into the method process of L1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of C1 into L1 as this is the use of a known technique to improve the removal process of layers within a device and therefore yields predictable results. The process of laser annealing provides a precise and efficient way of removing layers withing devices and is favorable process to not harm the internal structure of the device while still removing layers. The use of a known technique to improve a device yields predictable results (see C1 [0015] and [0017]).
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Regarding Claim 11, L1 and C1 disclose the method of claim 10 where L1 further discloses further comprising:
patterning the third semiconductor layer, the fourth semiconductor layer, the bonded layer, the second semiconductor layer, and the first semiconductor layer to define a fin (see FIG. 4, element 210, and [0018] ln. 3 “the stack 204 and a portion of the substrate 202 are patterned to form the fin-shaped structure 210”) extending upwards from the first substrate (The fins 210 extend upward from the substrate element 202 as seen in FIG. 4).
Regarding Claim 12, L1 and C1 disclose the method of claim 11 where L1 further discloses further comprising:
patterning source/drain recesses in the fin (see FIG. 4, elements 210 SD, 224-1, and 224-2, and [0021] ln. 1 “source/drain regions 210 SD of the fin-shaped structure 210 are recessed to a first source/drain recess 224 - 1 and a second source/drain recess 224 – 2”);
forming first source/drains (see FIG. 8, element 228, 228-1, and 228-2, and [0023] ln. 2 “first bottom source/drain feature 228-1 and a second bottom source/drain feature 228–2”) in the source/drain recesses (In FIG. 14, the source/drain features are in the recesses provided by elements 224);
depositing a first isolation layer over the first source/drains (see FIG. 8, element 242, [0025] ln. 3 “separation layer 242 may also be referred to as an isolation layer 242 as it functions to separate or isolate the bottom source/drain features 228”); and
forming second source/drains in the source/drain recesses over the first isolation layer (see FIG. 9, element 248-1, and [0026] ln. 2 “where a first top source/drain feature 248-1 is formed in the first source/drain recess 224–1”).
Regarding Claim 14, L1 and C1 disclose the method of claim 10, where C1 discloses wherein the laser anneal process (element 68) comprises using a laser beam that is emitted from a laser to heat the first de-bond layer, the first silicon layer, and the second de-bond layer (see [0050] for the laser removal process).
Regarding Claim 15, L1 and C1 disclose the method of claim 14, where C1 discloses wherein the laser operates in an infrared region (element 68) with a wavelength that is in a range from 500 to 2500 nm (see [0020] ln. 10 “using an Infrared (IR) laser having wavelengths in the range between about 1,800 nm and about 2,200 nm” which is in the presented range).
Regarding Claim 16, L1 and C1 disclose a method (see FIGs. 1-20 [0005-0006] ln. 1 “FIG. 1 illustrates a flow chart of a method for forming a semiconductor device…FIGS. 2-20 illustrate fragmentary cross-sectional views of a workpiece undergoing various fabrication processes in the method of FIG. 1) comprising:
forming a first de-bond structure ([0015] “the stack 204 includes a plurality of channel layers 208 interleaved by a plurality of sacrificial layers 206” where these elements make up a de-bond structure) over a first substrate (see FIG. 2, element 202, and [0014] ln. 2 “the workpiece 200 may include a substrate 202” where the elements 206 and 208 are over the substrate 202), wherein the first de-bond structure comprises a resonant cavity (see FIG. 2, and [0015] ln. 7 “the sacrificial layers 206 allow selective removal or recess of the sacrificial layers 206 without substantial damages to the channel layers 208” where a cavity can be formed in the described de-bond structure and see elements 224-1 and 224-2 [0021] ln. 3 “the fin-shaped structure 210 are recessed to a first source/drain recess 224 - 1 and a second source/drain recess 224 – 2”), and wherein the first de-bond structure comprises:
a first de-bond layer (see FIG. 2, element 206, [0015] ln. 3 “sacrificial layers 206”);
a first semiconductor layer over (see FIG. 2, element 208, and [0015] ln. 5 “the channel layers 208 are formed of silicon (Si)” where silicon is a semiconductor) the first de-bond layer (see FIG. 2 where element 206 is under element 208); and
a second de-bond layer over the first semiconductor layer (see FIG. 2 where a second element 206 is over the first 208);
epitaxially growing a first multi-layer stack (see FIG. 2, element 204T, [0016] ln. 13 “the stack 204 may be vertically divided into…top portion 204T”, where the layers included in this portion make up the first multi-layer stack) over the first de-bond structure (see FIG. 2 where the stack 204T is formed at the top of the stack 204);
bonding the first multi-layer (element 204T) stack to a second multi-layer stack (see FIG., 2 element 204M, [0016] ln. 14 “a middle portion 204M”); and
L1 does not disclose performing a first laser annealing process using a laser beam having a wavelength that matches a resonant frequency of the resonant cavity in order to ablate the first semiconductor layer and portions of the first de-bond layer and the second de-bond layer, and wherein performing the first laser annealing process results in a de-bonding of the first substrate from the first multi-layer stack.
C1 discloses performing a first laser annealing (see FIGs. 4 and 5, element 68, [0044] ln . 5 “laser beam 68” and [0050] for a description of the removal process) process using a laser beam having a wavelength (see [0020] ln. 10 “using an Infrared (IR) laser having wavelengths in the range between about 1,800 nm and about 2,200 nm”) that matches a resonant frequency of the resonant cavity (see FIG. 4, element 24, and [0019] ln. 2 “absorption layer 24 is formed of a material that may absorb the energy of laser” where the absorption layer 24 is the resonant cavity the laser 68 is pointed to for the laser process. Also see [0044] ln. 9 “laser beam 68 has the wavelength that allows it to be absorbed by absorption layer 24”)
C1 discloses in order to ablate the first semiconductor layer (see FIGs. 4 and 5, element 22, [0018] ln. 1 “layer 22… layer 22 is formed of a material that is transparent to the laser beam used in a subsequent de-bonding process… layer 22 is formed of or comprises an oxide-based material, which may be silicon oxide”) and portions of the first de-bond layer (see FIGs. 4 and 5, element 24, [0019] ln. 1 “absorption layer 24”) and the second de-bond layer (see FIGs. 4 and 5, element 26, [0026] ln. 1 “pad layer 26”) , and wherein performing the first laser annealing process results in a de-bonding of the first substrate (see FIGs. 4 and 5, element 20, and [0018] ln. 2 “base carrier 20”) from the first multi-layer stack (see FIGs. 4 and 5, where the base carrier 20 is removed from the multi-layer stack made by elements 22, 24, and 26, through the process of laser removal 68).
The laser removal process of one substrate as disclosed in C1 is incorporated into the method process of L1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of C1 into L1 as this is the use of a known technique to improve the removal process of layers within a device and therefore yields predictable results. The process of laser annealing provides a precise and efficient way of removing layers withing devices and is favorable process to not harm the internal structure of the device while still removing layers. The use of a known technique to improve a device yields predictable results (see C1 [0015] and [0017]).
Regarding Claim 17, L1 and C1 disclose the method of claim 16 further comprising:
L1 further discloses patterning the first multi-layer stack and the second multi-layer stack to form a fin (see FIG. 4, element 210, and [0018] ln. 3 “the stack 204 and a portion of the substrate 202 are patterned to form the fin-shaped structure 210”) , the fin comprising a plurality of lower nanostructures (see FIG. 5, element 204B, which now marks the nanostructure created by the patterning of the fin by elements 206 and 208) alternatingly stacked with first dummy nanostructures (elements 206 and 208 are alternately stacked within the stack 204B) and a plurality of upper nanostructures over the plurality of lower nanostructures (see FIG. 5, elements 204T and 204M, [0016] ln. 14 “middle portion 204M over the bottom portion 204B, and a top portion 204T), the plurality of upper nanostructures being alternatingly stacked with second dummy nanostructures (elements 206 and 208 are alternately stacked within the stack 204M and 204T);
replacing the first dummy nanostructures with a first gate stack (see FIG. 14, element 260, [0035] ln. 2 “gate structure 260”), the first gate stack surrounding each of the plurality of lower nanostructures (see FIG. 14, where the gate structures are in the lower portions of the fins 210, surrounding elements 206 and 208); and
replacing the second dummy nanostructures with a second gate stack (see FIG. 14 where the top nanostructure is also replaced by a gate structure 206), the second gate stack surrounding each of the plurality of upper nanostructures (see FIG. 14, where the gate structures are in the lower portions of the fins 210, surrounding elements 206 and 208).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0216340 A1), hereinafter as L1, and Chang et al. (US 2022/0406621 A1), hereinafter as C1, in view of Gao et al. (US 2019/0237540 A1), hereinafter as G1.
.
Regarding Claim 5, L1 and C1 disclose the method of claim 4, wherein but do not explicitly disclose during performing the first laser annealing process, the laser beam has a power output that is in a range from 500 mW to 5000 mW.
G1 discloses during performing the first laser annealing process, the laser beam has a power output that is in a range from 500 mW to 5000 mW (see [0094] ln. 3 “The laser splitting has the following requirements: an infrared laser is adopted…a laser power is 100mW-100w” where the laser used for splitting is within the IR requirement and consist the laser power range presented.
The IR laser as presented by G1 is incorporated into the disclosure of L1 and C1. It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to incorporate the disclosure of G1 into L1 and C1 as there is simple substitution of one element for another that yields predictable results – the specificity of the lasers power is paramount in laser use in splitting the device layers, and setting it this way ensures the layers are removed or split effectively. Using an IR laser at this power output is obvious and yields the predictable results (see G1 [0094] and [0102])
Regarding Claim 6, L1, C1, and G1 disclose the method of claim 5, wherein L1 and C1 discloses a resonant cavity (see L1, FIG. 5, elements 224-1 and 224-2, and [0021] ln. 4 “ first source/drain recess 224-1 and a second source/drain recess 224–2”) is formed in the combination of the first silicon layer, the first de-bond layer, and the second de-bond layer (elements 206 and 208 are removed to form this layer in combination), and wherein during the performing of the first laser annealing process, the laser interacts with the resonant cavity (see FIG. 3, [0018] ln. 24 “etch mask to etch the stack 204 and the substrate 202 to form the fin-shaped structure 210… etching process may include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes” where the formation of the fins creates the recesses 224) the laser interacts with the resonant cavity, (in this instance the laser etching of C1 is used for the etching of the recesses and fins as disclosed in C1).
Claims 7, 8, 13, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0216340 A1), hereinafter as L1, and Chang et al. (US 2022/0406621 A1), hereinafter as C1, in view of Ching et al. (US 2020/0176449 A1), hereinafter as C2.
Regarding Claim 7, L1 and C1 disclose the method of claim 1, wherein but does not explicitly disclose a thickness of each of the first de-bond layer and the second de-bond layer is in a range from 1 nm to 10 nm.
C2 discloses a thickness of each of the first de-bond layer and the second de-bond layer (see FIG. 2, elements 210, and 214 and [0030] ln. 4 “epitaxial stack 210 includes first epitaxial layers 214 of a first composition interposed” where there are multiple layers 214) is in a range from 1 nm to 10 nm (see [0033] ln. 1 “each of the first epitaxial layers 214 has a thickness range of about 2 nanometers” where de-bond layers have thickness values within the presented range).
The thickness values of the de-bond layer as presented by C2 are incorporated into the disclosure of L1 and C1. It would have been obvious at the time the invention was effectively filed to incorporate the disclosure of C2 into L1 and C1 due to there being motivation to alter the thickness of the de-bond layers in this fashion and yield predictable results. By confining the thickness values in this manner, proper support can be provided to the device without overcrowding the area. The motivation to have thickness values of this nature are beneficial to structural support and yield predictable results (see C2 [0033])
Regarding Claim 8, L1 and C1 disclose the method of claim 1, but do not explicitly disclose wherein a thickness of the first silicon layer is in a range from 5 nm to 200 nm.
C2 discloses wherein a thickness of the first silicon layer (see FIG. 2, element 216, and [0030] ln. 5 “second epitaxial layer 216… second epitaxial layers 216 are formed of silicon (Si)”) is in a range from 5 nm to 200 nm (see [0033] “second epitaxial layers 216 has a thickness range of about 5 nm to about 12 nm” which is within the presented range).
The thickness values of the silicon layer as presented by C2 are incorporated into the disclosure of L1 and C1. It would have been obvious at the time the invention was effectively filed to incorporate the disclosure of C2 into L1 and C1 due to there being motivation to alter the thickness of the de-bond layers in this fashion and yield predictable results. By confining the thickness values in this manner, proper support can be provided to the device without overcrowding the area. The motivation to have thickness values of this nature are beneficial to structural support and yield predictable results (see C2 [0033])
Regarding Claim 13, L1 and C1 disclose the method of claim 10, but do not disclose wherein a thickness of each of the first de-bond layer and the second de-bond layer is in a range from 1 nm to 10 nm.
C2 discloses wherein a thickness of each of the first de-bond layer and the second de-bond layer (see FIG. 2, elements 210, and 214 and [0030] ln. 4 “epitaxial stack 210 includes first epitaxial layers 214 of a first composition interposed” where there are multiple layers 214) is in a range from 1 nm to 10 nm (see [0033] ln. 1 “each of the first epitaxial layers 214 has a thickness range of about 2 nanometers” where de-bond layers have thickness values within the presented range).
The thickness values of the de-bond layer as presented by C2 are incorporated into the disclosure of L1 and C1. It would have been obvious at the time the invention was effectively filed to incorporate the disclosure of C2 into L1 and C1 due to there being motivation to alter the thickness of the de-bond layers in this fashion and yield predictable results. By confining the thickness values in this manner, proper support can be provided to the device without overcrowding the area. The motivation to have thickness values of this nature are beneficial to structural support and yield predictable results (see C2 [0033])
Regarding Claim 18, L1 and C1 disclose the method of claim 16, where L1 further comprises wherein the first semiconductor layer comprises silicon (see FIG. 2, element 208, and [0015] ln. 5 “the channel layers 208 are formed of silicon (Si)” where silicon is a semiconductor), and but neither disclose wherein a thickness of the first semiconductor layer is in a range from 5 nm to 200 nm.
C2 discloses wherein a thickness of the first semiconductor layer (see FIG. 2, element 216, and [0030] ln. 5 “second epitaxial layer 216… second epitaxial layers 216 are formed of silicon (Si)”) is in a range from 5 nm to 200 nm (see [0033] “second epitaxial layers 216 has a thickness range of about 5 nm to about 12 nm” which is within the presented range).
The thickness values of the silicon layer as presented by C2 are incorporated into the disclosure of L1 and C1. It would have been obvious at the time the invention was effectively filed to incorporate the disclosure of C2 into L1 and C1 due to there being motivation to alter the thickness of the de-bond layers in this fashion and yield predictable results. By confining the thickness values in this manner, proper support can be provided to the device without overcrowding the area. The motivation to have thickness values of this nature are beneficial to structural support and yield predictable results (see C2 [0033])
Regarding Claim 20, L1 and C1 disclose the method of claim 16, wherein but do not disclose a thickness of each of the first de-bond layer and the second de-bond layer is in a range from 1 nm to 10 nm.
C2 discloses a thickness of each of the first de-bond layer and the second de-bond layer (see FIG. 2, elements 210, and 214 and [0030] ln. 4 “epitaxial stack 210 includes first epitaxial layers 214 of a first composition interposed” where there are multiple layers 214) is in a range from 1 nm to 10 nm (see [0033] ln. 1 “each of the first epitaxial layers 214 has a thickness range of about 2 nanometers” where de-bond layers have thickness values within the presented range).
The thickness values of the de-bond layer as presented by C2 are incorporated into the disclosure of L1 and C1. It would have been obvious at the time the invention was effectively filed to incorporate the disclosure of C2 into L1 and C1 due to there being motivation to alter the thickness of the de-bond layers in this fashion and yield predictable results. By confining the thickness values in this manner, proper support can be provided to the device without overcrowding the area. The motivation to have thickness values of this nature are beneficial to structural support and yield predictable results (see C2 [0033])
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2022/0216340 A1), hereinafter as L1, and Chang et al. (US 2022/0406621 A1), hereinafter as C1, in view of Kim et al. (US 2019/0287846 A1), hereinafter as K1.
Regarding Claim 19, L1 and C1 disclose the method of claim 16, wherein but do not disclose the first de-bond layer and the second de- bond layer comprise yttrium oxide, cerium oxide, boron nitride or gallium phosphide.
K1 discloses the first de-bond layer and the second de-bond layer comprise yttrium oxide (see FIG. 1, element 220, and [0091] ln. 8 “insulating layer 220 formed from yttrium oxide”)
The insulating layer as disclosed by K1 is incorporated as the de-bond layer composition in L1 and C1. It would have been obvious at the time the invention was effectively filed to incorporate the disclosure of K1 into L1 and C1 due to there being motivation to include a material for bonding and de-bond that is able to be removed in the same manner it is attached. By using a material of this type, the de-bonding layer can be removed with less hassle. The motivation to use a bonding material of this composition is obvious and yields predictable results (see C2 [0033]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENNEN STUART CUDA whose telephone number is (571)272-6563. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/B.S.C./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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