DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Species III directed to Fig. 1C (claims 1-2, 4-10 and 12-19) in the reply filed on May 13rd, 2026 is acknowledged.
Claims 3 and 11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 7, 9, 12, 15 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 7 recites “a third underground interconnection line” in line 2 and “a third connecting via” in line 4. It is unclear to the examiner how the third underground interconnection line and the third connecting via exist without having the second underground interconnection line and the second connecting via within the semiconductor circuit structure.
Claim 7 recites the limitation “the depth” in lines 5 and 7. There is insufficient antecedent basis for this limitation in the claim.
Claim 9 recites the limitation “the depth” in lines 1 and 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation “the depth” in lines 5 and 7. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites “a fourth underground interconnection line” in line 2 and “a fourth connecting via” in line 4. It is unclear to the examiner how the fourth underground interconnection line and the fourth connecting via exist without having the second underground interconnection line and the second connecting via within the semiconductor circuit structure.
Claim 15 recites the limitation “the depth” in lines 1 and 3-4. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites “a second supply circuit” in line 2 and “a second signal generator” in line 3 while claims 16 and 19 fails to recite “a first supply circuit” and “a second signal generator”. It is unclear to the examiner how the second supply circuit and the second signal generator exist without having the first supply circuit and the first signal generator within the semiconductor circuit structure.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6, 8, 9, 16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (Pub. No.: US 2021/0028112 A1), hereinafter as Kim.
Regarding claim 1, Kim discloses a semiconductor circuit structure in Figs. 1-2 comprising: a semiconductor substrate (substrate 101) with an original semiconductor surface (upper surface of active fin 105) (see Fig. 2 and [0025]); a first set of PMOS transistors (each set of two active fins 105 and active region 102 for PMOS transistors) formed based on the semiconductor substrate (see Fig. 2 and [0026-0027]), and each PMOS transistor comprising a gate structure (gate structure GS), a first conductive region (one source/drain region 110), and a second conductive region (the other source/drain 110) (see Fig. 2 and [0028], [0058]); a first shallow trench isolation (STI) region (isolation layer 162B) neighboring to the first set of PMOS transistors and extending along a first direction (y-direction) (see Fig. 1-2 and [0030]); a first underground interconnection line (buried conductive wiring 120) within the first STI region and positioned under the original semiconductor surface, wherein the first underground interconnection line extends along the first direction (see Figs. 1-2 and [0033-0034]), and the first conductive region of each PMOS transistor is electrically connected to the first underground interconnection line (connected by second contact area 180B at contact CP) (see Figs. 1-2 and [0044]); and a first power voltage (a power voltage from ML2) electrically connected to the first underground interconnection line through a first connecting via (conductive through structure 250) (see Fig. 2 and [0036], [0049-0050]).
Regarding claim 4, Kim discloses the semiconductor circuit structure of claim 1, wherein the first conductive region of each PMOS transistor of the first set of PMOS transistors is connected to the first underground interconnection line through a corresponding connecting plug (connected by second contact area 180B) positioned within an active area (within active region 102) accommodating the corresponding PMOS transistor (see Figs. 1-2 and [0044]).
Regarding claim 6, Kim discloses the semiconductor circuit structure of claim 1, further comprising a second set of PMOS transistors (another set of two active fins 105 and active region 102 for PMOS transistors) formed based on the semiconductor substrate, each PMOS transistor of the second set of PMOS transistors comprising a gate structure (another gate structure GS), a first conductive region, and a second conductive region (another two source/drain 110) (see Figs. 1-2 and [0026], [0028], [0058]); wherein the first conductive region of each PMOS transistor of the second set of PMOS transistors is connected to the first underground interconnection line (connecting to the same buried conductive wiring 120 by contacts CP) (see Figs. 1-2 and [0044]).
Regarding claim 8, Kim discloses the semiconductor circuit structure of claim 1, further comprising: a first set of NMOS transistors another set of two active fins 105 and active region 102 for NMOS transistors) formed based on the semiconductor substrate, and each NMOS transistor comprising a gate structure (another gate structure GS), a first conductive region, and a second conductive region (see Figs. 1-2 and [0026], [0028], [0058]); a second STI region (another isolation layer 162B) neighboring to the second set of NMOS transistors and extending along the first direction; a second underground interconnection line (another buried conductive wiring 120) within the second STI region and positioned under the original semiconductor surface, wherein the second underground interconnection line extends along the first direction, and the second conductive region of each NMOS transistor is connected to the second underground interconnection line line (connected by another second contact area 180B at contact CP) (see Figs. 1-2 and [0044]); and a second power voltage (a power voltage from ML2 at another location) electrically connected to the second underground interconnection line through a second connecting via (another conductive through structure 250) (see Fig. 2 and [0036], [0049-0050]).
Regarding claim 9, Kim discloses the semiconductor circuit structure of claim 8, wherein the depth between the top surface of the first underground interconnection line and the original semiconductor surface is the same or substantially the same as the depth between the top surface of the second underground interconnection line and the original semiconductor surface (every buried conductive wiring 120 formed at the same depth) (see Fig. 2).
Regarding claim 16, Kim discloses a semiconductor circuit structure comprising: a semiconductor substrate (substrate 101) with an original semiconductor surface (upper surface of active fin 105) (see Fig. 2 and [0025]); a first set of circuit blocks (each set of two active fins 105 and active region 102 for PMOS transistors) formed based on the semiconductor substrate (see Fig. 2 and [0026-0027]); a first shallow trench isolation (STI) (isolation layer 162B) extending along the first set of circuit blocks (see Fig. 1-2 and [0030]); a first underground interconnection line (one buried conductive wiring 120) within the first STI region and positioned under the original semiconductor surface, wherein one terminal of each circuit block (source/drain region 110) is electrically connected to the first underground interconnection line (see Fig. 2 and [0028], [0058]); and a supply circuit (second wiring portion ML2) electrically connected to the first underground interconnection line and selectively transmitting a first predetermined signal to the first set of circuit blocks (a predetermine power voltage applied to ML2 transmitting to the set of PMOS transistor through conductive through structure 250 and buried conductive wiring 120) (see Fig. 2 and [0036], [0049-0050]).
Regarding claim 18, Kim discloses the semiconductor circuit structure of claim 16, wherein the first predetermined signal is a power signal (power signal from power line) and the first signal generator is a power source (power lines from power source) (see [0049]).
Allowable Subject Matter
Claims 2, 5, 10, 12, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 7, 12 and 19 will objected to as being dependent upon a rejected base claim, but would be allowable if amended to overcome 112 rejection and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
Wherein the first connecting via is extended from the original semiconductor surface to the first underground interconnection line as recited in claim 2.
The connecting plug is contacted to a sidewall of the first underground interconnection line as recited in claim 5.
Further comprising a third underground interconnection line under the original semiconductor surface and electrically connected to the first underground interconnection line through a third connecting via, wherein the depth between the top surface of the first underground interconnection line and the original semiconductor surface is different from the depth between the top surface of the third underground interconnection line and the original semiconductor surface as recited in claim 7.
Wherein the second connecting via is extended from the original semiconductor surface to the second underground interconnection line as recited in claim 10.
Further comprising a fourth underground interconnection line under the original semiconductor surface and electrically connected to the second underground interconnection line through a fourth connecting via, wherein the depth between the top surface of the second underground interconnection line and the original semiconductor surface is different from the depth between the top surface of the fourth underground interconnection line and the original semiconductor surface as recited in claim 12.
Wherein the supply circuit comprises a first switch between the first underground interconnection line and a first signal generator configured to generate the first predetermined signal, the first signal generator is electrically connected to the first switch through a first connecting via, and the first switch is electrically connected to the first underground interconnection line, wherein the first predetermined signal is selectively transmitted to the first set of circuit blocks through the first switch as recited in claim 17.
Further comprising: a second supply circuit comprising a second switch between the first underground interconnection line and a second signal generator, the second signal generator is electrically connected to the second switch through a second connecting via, and the second switch is electrically connected to the first underground interconnection line, wherein a second predetermined signal generated by the second signal generator is selectively transmitted to the first set of circuit blocks through the second switch as recited in claim 19.
Claims 13-14 are allowed over prior art of record.
Claim 15 will be allowed over prior art of record if rewritten to overcome the 112 rejections as set forth in the office action.
The following is an examiner' s statement of reason for allowance: the prior art made of record does not teach or fairly suggest the following:
A power gating switch between the first underground interconnection line and the second underground interconnection line, wherein the power gating switch selectively transmits the voltage value of the first power source from the second underground interconnection line to the first underground interconnection line as recited in claim 13. Claims 14-15 depend on claim 13, and therefore also include said claimed limitation.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818
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