DETAILED ACTION
1. Claims 1-9 are pending in this application filed on February 20, 2024
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Drawings
3. Drawings have been amended. However, they are insufficient to overcome the objection as discussed below.
Claim Rejections - 35 USC § 112
4. Claim 1 has been amended. Corresponding rejection is withdrawn.
Drawings
5. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Claim 1 requires the ground end of the first inverter of the word line driver to be connected with an external ground voltage (VSS). However, Figure 1 shows the ground end of the first converter connected to WL_VSS. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claims 1, 2, and 7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub. 2013/0010531 (“Huang”).
8. With respect to claim 1, Huang discloses a static random-access memory (FIG. 3), comprising
a sleep mode control module (320) and a memory cell array module (310),
wherein each row of the memory cell array module comprises M memory cells (311-31K) and one word line driver (FIGs. 7A, 7B), M being a positive integer;
the sleep mode control module comprises
a word line drive power supply module, and the word line drive power supply module comprises a power switch transistor (FIG. 7A, 808);
the word line driver comprises a first inverter (FIG. 7B, 830) and a second inverter (840);
the first inverter has an input end for connecting with a word line decode signal (DEC) (ZSEL), an output end connected with an input end of the second inverter (WLB), a power end connected with an external operating power supply (VDD) (VDD), and a ground end connected with an external ground voltage (VSS) (see FIGs. 7A and 7B, NGWLS is connected to GND via 806);
the second inverter has an output end connected with a word line (WL) of the M memory cells of the corresponding row (WL), a power end connected with a word line drive internal voltage node (WL_VDD) (NGWLD), and a ground end connected with the external ground voltage (VSS) (GND);
the power switch transistor (FIG. 7A, 808) of the word line drive power supply module of the sleep mode control module has one end connected with the word line drive internal voltage node (WL_VDD) (NGWLD) and the other end connected with the external operating power supply (VDD) (VDD); and
after the static random-access memory enters a sleep mode, a sleep logic enable signal controls the power switch transistor of the word line drive power supply module to be off, so that the power end of the second inverter is disconnected from the external operating power supply (VDD), in which case no power is supplied to the second inverter of the word line driver (paragraph [0051]); when the static random-access memory returns to a normal operating mode, the sleep logic enable signal controls the power switch transistor of the word line drive power supply module to be on, so that a power end of the word line driver is connected with the external operating power supply (VDD) to restore power supply to the second inverter of the word line driver (paragraph [0050]).
9. With respect to claim 2, Huang discloses the static random-access memory according to claim 1,
wherein the second inverter (FIG, 7B, 840) comprises a first drive PMOS transistor (Pd1) (818) and a first drive NMOS transistor (Nd1) (820);
a gate end of the first drive PMOS transistor (Pd1) and a gate end of the first drive NMOS transistor (Nd1) are short-connected to act as the input end of the second inverter (WLB);
a drain end of the first drive PMOS transistor (Pd1) and a drain end of the first drive NMOS transistor (Nd1) are short-connected to act as the output end of the second inverter (WL);
a source end of the first drive NMOS transistor (Nd1) acts as the ground end of the second inverter (GND); and a drain end of the first drive PMOS transistor (Pd1) acts as the power end of the second inverter (NGWLD).
10. With respect to claim 7, Huang discloses the static random-access memory (FIG. 2) according to claim 1, wherein
the memory cell comprises a zeroth transmission NMOS transistor (NPG0) (212), a first transmission NMOS transistor (NPG1) (214), a zeroth pull-up PMOS transistor (PPU0) (202), a first pull-up PMOS transistor (PPU1) (206), a zeroth pull-down NMOS transistor (NPD0) (204), and a first pull-down NMOS transistor (NPD1) (208);
a gate end of the zeroth transmission NMOS transistor (NPG0) and a gate end of the first transmission NMOS transistor (NPG1) are short-connected to the word line (WL), and a drain end of the zeroth transmission NMOS transistor and a drain end of the first transmission NMOS transistor (NPG1) are connected with complementary bit lines (BL, BLB) (see FIG. 2);
a source end of the zeroth pull-up PMOS transistor (PPU0) and a source of the first pull-up PMOS transistor (PPU1) are jointly connected with the external operating power supply (VDD), a drain end of the zeroth pull-up PMOS transistor (PPU0), a drain end of the zeroth pull-down NMOS transistor (NPD0), a gate end of the first pull-up PMOS transistor (PPU1), and a gate end of the first pull-down NMOS transistor (NPD1) are short-connected to a source end of the zeroth transmission NMOS transistor (NPG0), and a gate end of the zeroth pull-up PMOS transistor (PPU0), a gate end of the zeroth pull-down NMOS transistor (NPD0), a drain end of the first pull-up PMOS transistor (PPU1), and a drain end of the first pull-down NMOS transistor (NPD1) are short-connected to a source end of the first transmission NMOS transistor (NPG1); and the zeroth pull-down NMOS transistor (NPD0) and the first pull-down NMOS transistor (NPD1) are short-connected to act as a ground end (VSSCORE) of the memory cell (see FIGs. 2 and 3).
Claim Rejections - 35 USC § 103
11. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Huang.
Huang discloses all of the limitations of the parent claim 1 as discussed above. Huang discloses K memory cells, where K represents any number teaching the limitation of claim 9 “wherein M is 8, 16, 32, or 64.” To the extent Huang does not specifically mention a specific number of cells, it would have been obvious to one or ordinary skill in the art at the time of the invention to chose a specific number of cells, such as 8, 16, 32, and 64 as a matter of design choice.
Allowable Subject Matter
13. Claims 3-6 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
14. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Woo H Choi whose telephone number is (571)272-4179. The examiner can normally be reached 9 am - 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached on (571) 272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Woo H Choi/
Primary Examiner,
Art Unit 3992
