Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Final office action based on application 18/582,323 in response to reply filed July 6, 2026. Claims 1-16 are currently pending and have been considered below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-13, & 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bragaglia (Pre-Grant Publication 2021/0125043) in view of Chung (Pre-Grant Publication 2019/0165045).
Regarding claim 1, Bragaglia discloses a electrochemical device comprising:
a fin/channel pattern (Fig. 4, 12) arranged over an active region (10) extending in a first direction;
an interface layer (11 & 14) disposed on upper and sidewall surface of the fin/channel (12).
a gate (22) configured to partially wrap around upper and sidewall surfaces of each of the fin;
wherein the fin/channel can comprise a transition metal oxide such as WO3/tungsten oxide or SrTiO/strontium titanate oxide with a resistance that varies in response to gate voltage applied to the gate in a memory operation (Paragraph [0035, & 0037-0038]).
Bragaglia does not disclose a plurality of nano patterns spaced apart in a first direction and the interface layer & gate disposed on the upper, lower, and sidewall surfaces of the nano patterns. However, Chung discloses gate all around programmable memory device comprising:
A gate all around structure (Fig. 2(g2)) wherein a plurality of nano patterns/wires arranged over an active region spaced apart in a first direction, wherein a gate dielectric/interface layer & a gate electrode surrounds upper, lower and sidewall surface of each of the nano patterns to program different resistance states by applying voltage (Paragraph [0027]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the memory device as a gate all around structure including a plurality of nano patterns spaced apart having a interface/gate electrode disposed around upper, lower, and sidewall surface of the nano patterns because it will allow the gate increased control of the channel to alleviate short channel effects and with increased driving capability (Paragraph [0010]).
Regarding claim 2, Bragaglia further discloses:
the interface layer comprises an electrolyte layer (14) configured to exchange ions with the nano patterns in accordance with the gate voltage. (Paragraph [0033]).
Regarding claim 3 & 4, Bragaglia further discloses:
at least one of the electrolyte layer and the gate comprises an ion component and a metal, and the electrolyte layer comprises an insulation material (Paragraph [0033 & 0038]).
Regarding claim 5, Bragaglia further discloses:
the interface layer further comprises an ion storage layer (11) disposed between the electrolyte layer and the gate.
Regarding claim 7, Bragaglia further discloses:
at least one of the nano patterns, the gate and the interface layer comprises a material configured to generate ions in an electrochemical reaction based on a voltage applied to the gate (Paragraph [0033 & 0034]).
Regarding claim 8 & 9, Bragaglia discloses a neural network memory device comprising:
a plurality of electrochemical memory cells (Fig. 5; Paragraph [0063]), each of the electrochemical memory cells comprising: a lower layer (10) including an active region (12);
a channel region (12) disposed on a portion of the active region;
a source (21) arranged on the active region common to one end of the channel region;
a drain (23) arranged on the active region common to the other end of the channel region;
a gate (22) extending in a first direction to partially surround surfaces of the channel region; and
an interface layer (11/14) between the channel region and the gate, wherein the gate and interface layer are partially wrapped around the channel region (12).
The active region extends in a second direction intersecting the first direction (Fig. 4).
The channel region comprises a variable resistance pattern (12) comprising a transition metal oxide such as WO3/tungsten oxide or SrTiO/strontium titanate oxide whose resistance is variable in response to a gate voltage applied to the gate (Paragraph [0035, & 0037-0038])
Bragaglia does not disclose the channel region comprises a plurality of variable resistance patterns stacked in a third direction that is substantially perpendicular to the first and second directions. However, Chung discloses gate all around programmable memory device comprising:
A gate all around structure (Fig. 2(g2)) wherein a plurality of variable resistance patterns/nanowires arranged over an active region stacked in a third direction perpendicular to first and second direction wherein a gate surrounds upper, lower and sidewall surface of the nano patterns to program different resistance states by applying voltage (Paragraph [0027]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the memory device as a gate all around structure including a plurality of variable resistance patterns because it will allow the gate increased control of the channel to alleviate short channel effects and with increased driving capability (Paragraph [0010]).
Regarding claim 10, Bragaglia further discloses:
the interface layer comprises: an electrolyte layer (10; Paragraph [0033]) on the variable resistance patterns and including an insulation material; and
an ion storage layer (11) between the electrolyte layer and the gate that generates ions based on a direction of an electric field between the channel region and the gate and that receives and stores ions from the variable resistance patterns.
Regarding claim 11, Bragaglia further discloses:
the electrolyte layer transfers, exchanges or blocks ions between the gate and the variable resistance patterns based on the electric field (Paragraph [0033])
Regarding claim 12, Bragaglia further discloses:
the variable resistance patterns, the gate and the ion storage layer comprise a material that generates ions in an electrochemical reaction in accordance with the electric field (Paragraph [0033, 0037, 0038]).
Regarding claim 13, Bragaglia further discloses:
the ion storage layer comprises a material having an oxidation potential energy lower than an oxidation potential energy of the variable resistance patterns (Paragraph [0037 & 0038]).
Regarding claim 16, Bragaglia and Chung disclose all of the limitations of claim 8. Chung further discloses:
The source and drain comprises epitaxial pattern (Fig. 2f).
At least word line (Fig. 6 (d2), WL) extending in the first direction and connected to the gate;
at least one bit line (BL) extending in the second direction and connected to the drain; and
at least one source line (SL) extending in at least one of the first and second directions and connected to the source, wherein the electrochemical memory cells are positioned at intersected portions between the word line and the bit line (Paragraph [0127]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the source and drain as epitaxial pattern because it will provide area for adjacent contacts (Paragraph [0008]). Further by coupling a word line, bit line and source line to the gate, source, drain terminals will allow for the voltages to be applied to the varies lines to program the memory device by programming a high/low resistance state (Paragraph [0127]).
Claim(s) 6 & 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bragaglia (Pre-Grant Publication 2021/0125043) in view of Chung (Pre-Grant Publication 2019/0165045) as applied to claim 8 above, and further in view of Mokhtarzadeh (Pre-Grant Publication 2022/0059668).
Regarding claim 6 & 14-15, Bragaglia and Chung disclose all of the limitations of claim 1 & 8 (addressed above). Bragaglia further discloses:
a source (21) disposed on the active region and positioned in a second direction perpendicular to the first direction at one side of the channel region (12); and a drain (23) disposed on the active region and positioned in the second direction at an other side of the channel region.
Neither reference explicitly discloses the source and drain comprises a material different from a material in the nano patterns or each of the variable resistance patterns has a width extending in the first direction and a length extending in the second direction, and the width and the length of the variable resistance patterns is 0.1 to 50 nano meter. However, Mokhtarzadeh discloses a transistor device comprising:
A gate all around transistor device having source and drain regions (Fig. 7a, 106/107) positioned on opposite end of a plurality of nanowires (110) wherein the source/drain region can be epitaxially grown from substrate/active region (102) thereby comprising the same material and can comprise a material different than the nanowires (Paragraph [0050]).
Further the width of the nanowires (Fig. 7b, 110) can be 5-50 nanometer and a thickness/length can be 4-20 nanometers (Paragraph [0045]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the nanowires having a width and length of those dimensions because it will form a transistor device having enhance carrier mobility and improve device performance (Paragraph [0044]). Further by forming the source/drain to comprise a different material than the nanopatterns will serve to provide additional force/stress in the nanopattern to improve device performance (Paragraph [0050]).
Response to Arguments
Applicant's arguments filed July 6, 2026 have been fully considered but they are not persuasive. Applicant argument that the interface layer of Bragaglia is disposed only on the upper and side surface of the channel region is not considered persuasive because Chung disclose the advantages of using a Finfet type structure to be configured as a gate all around type structure such as allow the gate increased control of the channel to alleviate short channel effects and with increased driving capability (Chung Paragraph [0010]). Therefore, the device of Bragaglia can be modified as a gate all around structure wherein the interface layer and gate electrode would be disposed on the upper, lower and sidewalls of the plurality of nano patterns. Further applicant argument that Bragaglia does not disclose the nano pattern comprising a transition metal oxide whose resistance is variable in response to a gate voltage is not considered persuasive because Bragaglia disclose the material of channel region (12) can be materials such as WO3/tungsten oxide or SrTiO/strontium titanate oxide which would be material consistent with paragraphs [0038 & 0042]) of applicant specification of transition metal oxide materials.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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