Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
Applicant’s amendment dated 02/18/2026 in which claims 1-4, 6, 7, and 9 were amended has been entered of record. Currently, claims 1-9 are pending in light of the amendment.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kim (Patent Application Publication 2012/0221880).
Claim 1. A memory system comprising: a nonvolatile memory device (memory system MSYS comprises controller CNT and memory devices MDEV1-MDEVn, Kim [0040] and Fig 1) including a memory block including a first memory region coupled to an upper word line and a second memory region coupled to a lower word line a (data is written to chips MC1-MC4, [0092] Fig 17), and a controller (as seen in Fig 17) configured to (configured to is functional language) provide, together with a single program command (Data triggered by single command CMD, Kim FIG 17), first data to be stored in the first memory region and second data to be stored in the second memory region to the nonvolatile memory device (controller transmits DTA and command, to first and second region in memory chips Fig 17).
Claim 2. The memory system of claim 1, wherein the nonvolatile memory device is performs, after receiving the first data and the second data (sequential receipt as addressed in claim 1), a first program operation of storing the first data into the first memory region and a second program operation of storing the second data into the second memory region (program operations taught in Kim [0042] Fig 2).
Claim 3. The memory system of claim 1, wherein the nonvolatile memory device performs, before performing the second program operation, a verify operation of identifying data that have been stored in the second memory region (Verify sense operations taught in Kim [0042] Fig 2).
Claim 4. The memory system of claim 2, wherein the nonvolatile memory device performs the first program operation and the second program operation in response to the single program command (as taught by Kim [0098-0101] and Fig 20-21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (Patent Application Publication 2012/0221880) in view of Towika (Patent Application Publication 2011/0066900).
Kim discloses the memory system of claim 1 but does not disclose programming LSB and MSB (programing data to different states).
Towika discloses programming to 0 and 1 (Tokiwa [0072,0073]) for the purpose of improving storage density and enabling multi level storage (programming multiple states 0 and 1 Towika [0072-0073], operations performed separately or in parallel, Towika [0088]).
Since Towika and Kim are both from the same field of endeavor (NAND nonvolatile memory), the purpose disclosed by Towika would have been recognized in the pertinent art of Kim.
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to use the different data states as representing different bit significance (LSB/MSB) for the purpose of improving storage density and enabling multi level storage.
Claim 6. The memory system of claim 1 (Kim teaches the memory system of claim 1 as addressed above), wherein the lower word line and the upper word line are adjacent to each other (adjacent wordlines WL0 and WL1 are adjacent to one another in a memory array, Towika Fig 3, same motivation to combine as claim 5).
Claim 7. The memory system of claim 1 (Kim teaches the memory system of claim 1 as addressed above), wherein the lower word line is closer to a source line than the upper word line (Lower wordlines like WL0 are below upper wordlines WL1 WL2 placing the lower wordlines closer to the underlying structure, Towika Fig 3, same motivation to combine as claim 5).
Claim 8. The memory system of claim 1 (Kim teaches the memory system of claim 1 as addressed above), wherein the first memory region and the second memory region are disposed in a common plane (layers MA0-MA3 form a plane in which cells are at the intersection of wordlines and bit lines, Towika [0062] Fig 2, same motivation to combine as claim 5).
Claim 9. The memory system of claim 1 (Kim teaches the memory system of claim 1 as addressed above), wherein the nonvolatile memory device is a first nonvolatile memory device (memory devices MDEV1-MDEVn are non volatile memory, Kim Fig 1), and the single program command is a first single program command (Data triggered by single command CMD, Kim FIG 17), the system further comprising a second nonvolatile memory device, and wherein the controller provides the first data and the second data to the first nonvolatile memory device and then provides third data and fourth data to the second nonvolatile memory device together with the single program command (together with a single command CMD Fig 27. Data is associated with the same command even when sent sequentially), such that the first nonvolatile memory device and the second nonvolatile memory device operate in parallel (Kim teaches multiple memory devices and parallel operation [0040] [0060]. Towika teaches program operations performed simultaneously in parallel [0080]. The combination teaches multiple sets of data to multiple mem devices and performing operation in parallel, same motivation to combine as claim 5).
Response to Arguments
Applicant's arguments with respect to claims 1-9 have been considered but are moot in view of the new ground(s) of rejection.
Newly amended claim 1 and dependent claims 2-4 are addressed in the 102 above.
Claims 5-9 are addressed in the 103 above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason Lappas whose telephone number is (571) 270-1272. The examiner can normally be reached on M-F 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON LAPPAS/Primary Examiner, Art Unit 2827
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