DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,5-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2008/0290477 A1 to Muramatsu et al., “Muramatsu”.
Regarding claim 1, Muramatsu discloses an array of strips (e.g. Fig. 2 interconnect frame 10) of interconnects comprising:
a first set of strips (“B” in region 10A including 12u,12v,12w, ¶ [0077]-[0019]) of interconnects in the array of strips of interconnects; and
a second set of strips (“A” in region 10A including 11u,11v,11w, ¶ [0077]-[0079]) of interconnects in the array of strips of interconnects; wherein:
strips of interconnects of the first set of strips of interconnects have a first distance (as shown in Fig. 2 but easier seen after trimming in Fig. 6 in Examiner-annotated figure below) between an edge of a respective strip of interconnects of the first strip of interconnects and a pin (lead 15) closest to the edge of the respective strip of interconnects of the first strip of interconnects, and
strips of interconnects of the second set of strip of interconnects are adjacent to strips of interconnects of the first set of strips of interconnects (as pictured), and the strips of interconnects of the second set of strips of interconnects have a second distance (see Examiner-annotated figure below) between an edge of a respective strip of interconnects of the second set of strips of interconnects and a pin (14) closest to the edge of the respective strip of interconnects of the second set of strips of interconnects, the first distance being different than the second distance; and
pins (15 and 17, ¶ [0084],[0085]) of the first set of strips of interconnects in the array of strips of interconnects are interleaved with the pins (14 and 16, ¶ [0084],[0085]) of the second set of strips of interconnects in the array of strips of interconnects.
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Regarding claim 2, Muramatsu discloses the array of strips of interconnects of claim 1, and Muramatsu further discloses wherein the pins (15 and 17) in the first set of strips of interconnects and the pins (14 and 16) in the second set of strips of interconnects are trimmed (trimmed between Fig. 5A to Fig. 6, ¶ [0051],[0052]) and formed (Fig. 7A, ¶ [0053]).
Regarding claim 5, Muramatsu discloses the array of strips of interconnects of claim 1, and Muramatsu further discloses wherein the first set of strips of interconnects and the second set of strips of interconnects comprise die pads (Fig. 3 locations of Thx, Du, Thy, Dv, Thz, Dw, and Dx, Dy, Dz) for dies of an integrated circuit (IC) chip (¶ [0069],[0070]).
Regarding claim 6, Muramatsu discloses the array of strips of interconnects of claim 5, and Muramatsu further discloses dies (Thx, Du, Thy, Dv, Thz, Dw, and Dx, Dy, Dz) attached to respective ones of the die pads.
Regarding claim 7, Muramatsu discloses the array of strips of interconnects of claim 6, and Muramatsu further discloses bond wires (e.g. wires 30,31,32, ¶ [0095]) between contacts on the dies (Thx, Du, Thy, Dv, Thz, Dw, and Dx, Dy, Dz) and bond pads of the pins of the first (15 and 17) and second (14 and 16) sets of strips of interconnects.
Regarding claim 8, Muramatsu discloses the array of strips of interconnects of claim 7, and Muramatsu further discloses a respective bar of molding material (42 and 41, ¶ [0097]) covering the dies, bond pads and die pads in each of the strips of interconnects.
Regarding claim 9, Muramatsu discloses the array of strips of interconnects of claim 8, and Muramatsu further discloses wherein the molding material is plastic (resin, ¶ [0097]).
Regarding claim 10, Muramatsu discloses the array of strips of interconnects of claim 5, and Muramatsu further discloses wherein the interconnects for dies of the IC chips are dual in-line package interconnects (as pictured, ¶ [0011],[0012]).
Regarding claim 11, Muramatsu discloses the array of strips of interconnects of claim 8, and Muramatsu further discloses wherein the pins (15 and 17) in the first set of strips of interconnects and the pins (14 and 16) in the second set of strips of interconnects are trimmed (trimmed between Fig. 5A to Fig. 6, ¶ [0051],[0052]) and formed (Fig. 7A, ¶ [0053]).
Regarding claim 12, Muramatsu discloses the array of strips of interconnects of claim 11, and Muramatsu further discloses wherein the first distance is greater than the second distance (as pictured in Examiner-annotated figure with claim 1 above).
Regarding claim 13, Muramatsu discloses an array of strips of interconnects comprising:
strips of interconnects of a first set (“B” in region 10A including 12u,12v,12w, ¶ [0077]-[0019]) of strips of interconnects having a first distance (as shown in Fig. 2 but easier seen after trimming in Fig. 6 in Examiner-annotated figure above with claim 1) between an edge of a respective strip of interconnects of the first strip of interconnects and a pin closest to the edge of the respective strip of interconnects of the first strip of interconnects;
strips of interconnects of a second set (“A” in region 10A including 11u,11v,11w, ¶ [0077]-[0079]) of strip of interconnects adjacent to the strips of interconnects of the first set of strips of interconnects, and the strips of interconnects of the second set of strips of interconnects having a second distance between an edge of a respective strip of interconnects of the second set of strips of interconnects and a pin closest to the edge of the respective strip of interconnects of the second set of strips of interconnects, the first distance being different than the second distance (see Examiner-annotated figure with claim 1 above); and
pins (15 and 17, ¶ [0084],[0085]) of the first set of strips of interconnects in the array of strips of interconnects are interleaved with the pins (14 and 16, ¶ [0084],[0085]) of the second set of strips of interconnects in the array of strips of interconnects.
Regarding claim 14, Muramatsu discloses the array of strips of interconnects of claim 13, and Muramatsu further discloses wherein the first set of strips of interconnects and the second set of strips of interconnects comprise die pads (Fig. 3 locations of Thx, Du, Thy, Dv, Thz, Dw, and Dx, Dy, Dz) for dies of an integrated circuit (IC) chip (¶ [0069],[0070]).
Regarding claim 15, Muramatsu discloses the array of strips of interconnects of claim 14, and Muramatsu further discloses dies (Thx, Du, Thy, Dv, Thz, Dw, and Dx, Dy, Dz) attached to respective ones of the die pads.
Regarding claim 16, Muramatsu discloses the array of strips of interconnects of claim 15, and Muramatsu further discloses bond wires (e.g. wires 30,31,32, ¶ [0095]) between contacts on the dies (Thx, Du, Thy, Dv, Thz, Dw, and Dx, Dy, Dz) and bond pads of the pins of the first (15 and 17) and second (14 and 16) sets of strips of interconnects.
Regarding claim 17, Muramatsu discloses the array of strips of interconnects of claim 16, and Muramatsu further discloses a respective bar of molding material (42 and 41, ¶ [0097]) covering the dies, bond pads and die pads in each of the strips of interconnects.
Regarding claim 18, Muramatsu discloses the array of strips of interconnects of claim 17, and Muramatsu further discloses wherein the interconnects for dies of the IC chips are dual in-line package interconnects (as pictured, ¶ [0011],[0012]).
Regarding claim 19, Muramatsu discloses the array of strips of interconnects of claim 17, and Muramatsu further discloses wherein the pins (15 and 17) in the first set of strips of interconnects and the pins (14 and 16) in the second set of strips of interconnects are trimmed (trimmed between Fig. 5A to Fig. 6, ¶ [0051],[0052]) and formed (Fig. 7A, ¶ [0053]).
Regarding claim 20, Muramatsu discloses an array of bar molded strips of interconnects comprising:
bar molded strips of interconnects of a first set (“B” in region 10A including 12u,12v,12w, ¶ [0077]-[0019]) of strips of interconnects having a first distance (as shown in Fig. 2 but easier seen after trimming in Fig. 6 in Examiner-annotated figure above with claim 1) between an edge of a respective strip of interconnects of the first strip of interconnects and a pin closest to the edge of the respective strip of interconnects of the first strip of interconnects;
bar molded strips of interconnects of a second set (“A” in region 10A including 11u,11v,11w, ¶ [0077]-[0079]) of strip of interconnects adjacent to the strips of interconnects of the first set of strips of interconnects, and the strips of interconnects of the second set of strips of interconnects having a second distance (see Examiner-annotated figure with claim 1 above) between an edge of a respective strip of interconnects of the second set of strips of interconnects and a pin closest to the edge of the respective strip of interconnects of the second set of strips of interconnects, the first distance being different than the second distance (as pictured); and
pins (15 and 17, ¶ [0084],[0085]) of the first set of strips of interconnects in the array of strips of interconnects are interleaved with the pins (14 and 16, ¶ [0084],[0085]) of the second set of strips of interconnects in the array of strips of interconnects.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over US 2008/0290477 A1 to Muramatsu et al., “Muramatsu”, as applied to claim 2 above, and further in view of US 2017/0179008 A1 to Cari-an et al., “Cari-an”.
Regarding claim 3, although Muramatsu discloses the array of strips of interconnects of claim 2, Muramatsu fails to clearly teach wherein the array of strips of interconnects rest on a sawing chuck table.
Cari-an teaches (e.g. FIG. 5C) wherein an array of interconnects (lead frame) rest on a saw (165, ¶ [0035]) chuck table (167, ¶ [0037]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Muramatsu by placing the interconnect strips on a saw chuck table as exemplified by Cari-an in order to perform the sawing step with reduced blade heating during singulation (Cari-an Abstract, ¶ [0004],[0024],[0028],[0035]).
Regarding claim 4, Muramatsu in view of Cari-an yields the array of strips of interconnects of claim 3, and Muramatsu further teaches wherein the first distance is greater than the second distance (see Examiner-annotated figure with claim 1 above).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2017/0213784 A1 to Lee et al. teaches (FIG. 7) wherein a first set of pins (from e.g. “ODD COLUMN”) are interleaved with a second set of pins (from e.g. “EVEN COLUMN”);
US 20210225744 A1 to Singer et al. teaches (e.g. Fig. 28-30) first and second sets of interleaving pins (108);
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891
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