Prosecution Insights
Last updated: April 19, 2026
Application No. 18/582,549

REGISTRATION BETWEEN AN INSPECTION IMAGE AND A DESIGN IMAGE

Non-Final OA §101§102§103
Filed
Feb 20, 2024
Examiner
LI, RUIPING
Art Unit
2676
Tech Center
2600 — Communications
Assignee
Applied Materials Israel Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
95%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
722 granted / 933 resolved
+15.4% vs TC avg
Strong +18% interview lift
Without
With
+18.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
40 currently pending
Career history
973
Total Applications
across all art units

Statute-Specific Performance

§101
13.0%
-27.0% vs TC avg
§103
41.2%
+1.2% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
13.7%
-26.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 933 resolved cases

Office Action

§101 §102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status. 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 2. Claims 1-20 filed on 02/20/2024 are pending and being examined. Claims 1, 17, and 20 are independent form. Claim Rejections - 35 USC § 101 3. 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. 4. Claims 1- 20 are rejected under 35 U.S.C. 101 because the claimed inventions are directed to non-statutory subject matter (an abstract idea without significantly more). 4-1. Regarding independent claim 1, the claim recites a system comprising one or more processing circuitries configured to: [1] obtain an inspection image of a semiconductor specimen, and a design image or design data, informative of a plurality of design elements, [2] determine data Dpitch informative of a periodic distance between design elements of the plurality of design elements, which are associated with a shape meeting a similarity criterion, and [3] use the data Dpitch to obtain registration data between the design image or the design data, and the inspection image. Step 1: With regard to step (1), claim 1, is directed to a system comprising one or more processing circuitries. The claim 1 therefore is one of statutory categories of invention, i.e., a machine and/or manufacture. Step 2A-1: With regard to 2A-1, The elements recited in claim 1, as drafted, under their broadest reasonable interpretation, encompass a process(es) which is/are directed to organizing human activity, can be practically performed in human mind, or falls within mathematical concepts. For example, “determin[ing] data Dpitch informative of a periodic distance between design elements of the plurality of design elements, which are associated with a shape meeting a similarity criterion” in step [2] in the context of this claim, encompasses mental observation, evaluations, judgments, and/or opinions that “can be performed in human mind, or by a human using a pen and paper”, therefore the limitation falls within the “mental processes” grouping of abstract ideas. Similarly, “us[ing] the data Dpitch to obtain registration data between the design image or the design data, and the inspection image” in step [3] are mathematical calculations and fall within the “mathematical concepts” grouping of abstract ideas. Claim 1 therefore recites an abstract idea. If a claim limitation is directed to organizing human activity, can be practically performed in human mind, or falls within mathematical concepts, then the claim recites an abstract idea. See MPEP 2106.04(a)(2). Step 2A-2: The 2019 PEG defines the phrase "integration into a practical application" to require an additional element or a combination of additional elements in the claim to apply, rely on, or use the judicial exception. In the instant case, the additional elements of “obtain[ing] an inspection image of a semiconductor specimen, and a design image or design data, informative of a plurality of design elements” in step [1] under its broadest reasonable interpretation, is mere data gathering recited at a high level of generality, and thus are insignificant extra-solution activity. Similarly, “one or more processing circuitries” are recited at high level of generality and amount to no more than mere instruction to apply the exception using generic processor(s). Therefore, the claim as a whole does not integrate the judicial exception into a practical application. Step 2B: As explained above, the system comprising one or more processing circuitries, is at best the equivalent of merely adding the words “apply it” to the judicial exception. The “obtain[ing] an inspection image of a semiconductor specimen, and a design image or design data, informative of a plurality of design elements” in step [1] was considered insignificant extra-solution activity. These conclusions should be reevaluated in Step 2B. The limitations are mere data gathering and/or output recited at high level of generality and amount to receiving (i.e., acquiring), accessing, or transmitting data over a network, which is well-understood, routine, conventional activity. See MPEP 2106.05(d), subsection II. The limitations remain insignificant extra-solution activity even upon reconsideration. Even when considered in combination, the additional elements present mere instructions to apply an exception and insignificant extra-solution activity, which cannot provide an inventive concept. The claim therefore is ineligible. 4-2. Regarding dependent claims 2-16, they are dependent from claim 1 and viewed individually, these additional elements are under its broadest reasonable interpretation, either covers performance of the limitation in the mind, performing a mathematical algorithm or extra solution activity for data gathering and do not provide meaningful limitations to transform the abstract idea into a patent eligible application of the abstract idea such that the claims amount to significantly more than the abstract idea itself. And, when the claims are viewed as a whole, they do not improve a technology by allowing the technology to perform a function that it previously was not capable of performing; and they do not provide any limitations beyond generally linking the use of the abstract idea to a broad technological environment (i.e., computer-based analysis of generic data). Hence, the claimed invention does not constitute significantly more than the abstract idea, so the claims are rejected under 35 USC § 101 as being directed to non-statutory subject matter. 4-3. Regarding independent claims 17 and 20, the claims recite a system (claim 17) a non-transitory storage medium (claim 20) and each of which analogous to apparatus claim 1, grounds of rejection analogous to those applied to claim 1 are applicable to claims 17 and 20. Each of them therefore recites an abstract idea. 4-4. Regarding dependent claims 16-19, they are dependent from claim 17 and are viewed individually, these additional elements are under its broadest reasonable interpretation, either covers performance of the limitation in the mind, performing a mathematical algorithm or extra solution activity for data gathering and do not provide meaningful limitations to transform the abstract idea into a patent eligible application of the abstract idea such that the claims amount to significantly more than the abstract idea itself. And, when the claims are viewed as a whole, they do not improve a technology by allowing the technology to perform a function that it previously was not capable of performing; and they do not provide any limitations beyond generally linking the use of the abstract idea to a broad technological environment (i.e., computer-based analysis of generic data). Hence, the claimed invention does not constitute significantly more than the abstract idea, so the claims are rejected under 35 USC § 101 as being directed to non-statutory subject matter. Claim Rejections - 35 USC § 102 5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 7. Claims 1-4, 10-11, 16-18, and 20 are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Sakai et al (US2018/0012349, hereinafter “Sakai”). Regarding claim 1, Sakai discloses a system comprising one or more processing circuitries (“the pattern measurement apparatus that appropriately assesses patterns formed by patterning methods for forming patterns that do not exist on photomasks”, see abstract) configured to: obtain an inspection image of a semiconductor specimen, and a design image or design data, informative of a plurality of design elements (see 810 of fig.8 and para.60: “A pattern center-of-gravity calculation unit 810 extracts the position (coordinates) of the center of gravity of a pattern included in an SEM image from pattern data obtained on the basis of design data or simulation data...”), determine data Dpitch informative of a periodic distance between design elements of the plurality of design elements (see the method of registering grid line information using a SEM image shown by fig.4 and para.79: “nearby patterns at a minimum distance from the detected pattern coordinate group are detected (S411)”. Also, as an example, see “Pattern Pitch” 204 in fig.2), which are associated with a shape meeting a similarity criterion (see para.78: “since a semiconductor pattern is a pattern in which the same shape is repeated, it is possible to detect the position of the pattern by automatically recognizing the repetitive period by image processing or the like”), and use the data Dpitch to obtain registration data between the design image or the design data, and the inspection image (see S424 of fig.4 and para.82: “The grid line, the auxiliary grid line, and the reference line are corrected on the basis of recalculated information [including the designated reference line and the coordinates of the center of gravity of the detected reference pattern] and are displayed on the secondary electron image [i.e., the inspection (SEM) image] display apparatus 124 (S424)”. Also see fig.3 and para.72: “a distance from a measurement reference point 312 which is one of intersection points between the plurality of reference lines X and Y is calculated, and an amount of deviation 313 is output. Similarly, the processes are performed on all of the patterns within a screen, and the reference point 303 is aligned such that the total of the amounts of deviation is minimized (S603).”). Regarding claim 2, Sakai discloses the system of claim 1, wherein the design image or the design data are informative of a plurality of design layers, wherein the system is configured to determine, for each given design layer of the plurality of design layers, given registration data between the given design layer and the inspection image (see para.65: “the input apparatus 815 also has a function of collating coordinate information which is input and information regarding the type of pattern with layer information of design data and identification information of the pattern, and reading out necessary information from the design data storage medium 814.” See para.47: “the management of an overlay margin which is an importance management item in the manufacture of a semiconductor can be performed in accordance with an alignment error between different layers and the management of the dimension (critical dimension: CD) of a pattern.”). Regarding claim 3, Sakai discloses the system of claim 1, configured to determine a derivative signal corresponding to a derivative of a pixel intensity signal associated with the design image or with the design data, and to use the derivative signal to determine data Dpitch (see para.80: “Other pitch calculation methods to be considered include a method of obtaining a pitch according to a distance between peaks from projection waveforms in the X- and Y-directions and a direction in which a pattern is present”. It should be noticed that a peak detected includes detecting a derivative signal corresponding to a derivative of a pixel intensity signal). Regarding claim 4, Sakai discloses the system of claim 1, configured to determine a correspondence between the design image and the inspection image, for different shifts of the design image relative to the inspection image, wherein amplitude of the different shifts has been determined based on data Dpitch (see the deviation 313 between the reference (i.e., the design point) point 312 and the measurement point 311 in fig.3). Regarding claim 10, Sakai discloses the system of claim 1, configured to detect presence of one or more horizontal or vertical lines in the design image or in the design data (see the vertical lines 5803 and the horizontal lines 5804 of fig.19), and use this detection to determine the registration data between the design image or the design data and the inspection image (see S424 of fig.4 and para.82: “The grid line, the auxiliary grid line, and the reference line are corrected on the basis of recalculated information [including the designated reference line and the coordinates of the center of gravity of the detected reference pattern] and are displayed on the secondary electron image [i.e., the inspection (SEM) image] display apparatus 124 (S424)”.). Regarding claim 11, 18, Sakai discloses, wherein the registration data comprise: data informative of a shift of the design image or of the design data; data informative of a deformation of one or more of the plurality of design elements; and displacement parameters of one or more points of the design image or of the design data (see fig.3 and para.72: “a distance from a measurement reference point 312 which is one of intersection points between the plurality of reference lines X and Y is calculated, and an amount of deviation 313 is output. Similarly, the processes are performed on all of the patterns within a screen, and the reference point 303 is aligned such that the total of the amounts of deviation is minimized (S603).” It should be noticed that the deviation 313 may indicate a shift, a deformation, and a displacement parameter of the design data.). Regarding claim 16, Sakai discloses the system of claim 1, wherein the design data is informative of a plurality of design layers, wherein the system is configured to rasterize the design data of the plurality of design layers, and combine them to obtain the design image, without requiring user input for defining pixel intensity in the design image (see fig.3 and para.69: “a grid (measurement reference data) is superimposed on an SEM image (or a contour image obtained on the basis of the SEM image)... A grid arrangement screen 300 disposed on the secondary electron image display apparatus 124 is an image obtained by overlaying a reference line X 301 and a reference line Y 302 on the measurement pattern image 200.”). Regarding claims 17, 20, each of them essentially is an inherent variation of claim 1, thus it is interpreted and rejected for the reasons set forth in the rejection of claim 1. Claim Rejections - 35 USC § 103 8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 9. Claims 6, 9, 12, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Sakai in view of Kitamura et al (US 20110235895, hereinafter “Kitamura”). Regarding claim 6, Sakai does not explicitly disclose the claimed invention. However, in the same field of endeavor, Kitamura teaches, wherein each position of these successive positions differs from a previous position by a shift which is equal to or smaller than half said periodic distance (see fig.4 and para.240: “a shift quantity S1 is obtained, and the first reference pattern is shifted by the shift quantity S1. Next, by comparing the detected first edges with the edges of the first reference pattern shifted, the pattern to-be-inspected is inspected. In the first inspection, pattern deformation quantities are obtained by comparing the detected first edges with the edges of the first reference pattern, and then a defect is detected from the pattern deformation quantities. A shift quantity S2 is obtained as one of the pattern deformation quantities.”). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the teachings of Kitamura into the teachings of Sakai and obtain a shift quantity as one of the pattern deformation quantities taught by Kitamura. Suggestion or motivation for doing so would have been to inspect a pattern on a semiconductor integrated circuit (LSI). See, Abstract. Therefore, the claim is unpatentable over Sakai in view of Kitamura. Regarding claim 9, the combination of Sakai and Kitamura discloses, wherein the inspection image comprises a plurality of structural elements (see para.114: “an elliptical shape, a circular shape, or the like”), wherein the system is configured to perform at least one of (i) or (ii): (i) perform a reduction of noise present in the inspection image, wherein said reduction depends on one or more dimensions of the structural elements (Kitamura, see fig.104 which is a schematic view showing a method of reducing a noise on a contour), or (ii) perform an enhancing of edges of one or medgeore of the structural elements, wherein said enhancing depends on one or more dimensions of the structural elements. Regarding claim 12, the combination of Sakai and Kitamura discloses, configured to determine a deformation enabling a match between the design elements and structural elements of the inspection image according to a matching criterion (Kitamura, see para.32: “In a preferred aspect of the present invention, the inspection device inspects the pattern to-be-inspected by using deformation quantities for every pattern-to-be-inspected.”. See para.6: “Therefore, an allowable pattern deformation quantity should be set in order to ignore the above difference. As a result, a problem in which a fine defect existing in a place except a corner cannot be detected has happened.”). Regarding claim 15, the combination of Sakai and Kitamura discloses, wherein: the design image or the design data is informative of a plurality of design layers, the registration parameters are informative of at least one of: a shift, a deformation, or displacement parameters of one or more points of the design image (Kitamura, see fig.4 and para.240: “a shift quantity S1 is obtained, and the first reference pattern is shifted by the shift quantity S1. Next, by comparing the detected first edges with the edges of the first reference pattern shifted, the pattern to-be-inspected is inspected.), wherein the system is configured to use said registration parameters to transform each design layer separately (Kitamura, see para.708: “Then a position of the shifted second edge is registered as a position of a vertex of a contour.”). 10. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sakai in view of Kaneko (US2021/0042901, hereinafter “Kaneko”). Regarding claim 8, Sakai does not explicitly disclose the claimed invention. However, the die-to-database inspection is well-known and widely used in the field of wafer inspection. As evidence, Kaneko teaches, convert edges of the given design element into rounded edges, wherein a curvature of the rounded edges is selected based on one or more dimensions of the given design element (see para.2: “Scaling and line width-offset are uniformly applied in advance to the reference pattern in accordance with the wafer pattern, and a corner rounding process is applied for matching with the wafer pattern or detecting an edge.”). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to incorporate the teachings of Kaneko into the teachings of Sakai and apply a corner rounding process taught by Kaneko for matching with the wafer pattern or detecting an edge. Suggestion or motivation for doing so would have been to generate “a correction line indicating a relationship between an amount of deviation of an edge of a wafer pattern from an edge of a reference pattern and a width of a space adjacent to the edge of the reference pattern”. See, Abstract. Therefore, the claim is unpatentable over Sakai in view of Kaneko. Subject Matter Not Found in the Prior Art 11. The subject matter of claims 5, 7, 13, 14, and 19, in combination with the base claim and intervening claims, were not found in the prior art. Allowability is not indicated at this time due to the rejection under 35 U.S.C. 101. Conclusion 12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RUIPING LI whose telephone number is (571)270-3376. The examiner can normally be reached 8:30am--5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, HENOK SHIFERAW can be reached on (571)272-4637. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit https://patentcenter.uspto.gov; https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center, and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RUIPING LI/Primary Examiner, Ph.D., Art Unit 2676
Read full office action

Prosecution Timeline

Feb 20, 2024
Application Filed
Feb 26, 2026
Non-Final Rejection — §101, §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
95%
With Interview (+18.0%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 933 resolved cases by this examiner. Grant probability derived from career allow rate.

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