DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 07/01/2026 have been fully considered but they are not persuasive. Applicant argues on page 8 that the Meiser reference discloses that dielectric 42, not 43, is above temperature sensor diode 50. The Examiner disagrees as depending on the orientation either 42 or 43 is “above” the temperature sensor diode 50. Applicant’s specification describes terms like “upper” and “lower” as not limited to the gravity direction or a direction when a semiconductor is mounted (specification page 3 paragraph [0026]) and that orthogonal coordinate axes merely specify relative positions of components and do not limit a specific direction (specification page 3 paragraph [0027]). Regardless, Meiser shows the dielectric layers 42 and/or 43 are along the surfaces of the wider temperature sensor diode region 50 and narrower “longish section” 161’ and therefore satisfying the language of the protective film including a first region adjacent to the temperature sensing protective film, and a second region provided more spaced apart from the temperature sensing protective film than the first region and having a width narrower than that of the first region.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,4,7,10-12 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by U.S. 2014/0334522 A1 to Meiser et al., “Meiser”.
Regarding claim 1, Meiser discloses a semiconductor device (FIG 1,2,3,4,5) comprising:
a temperature sensing portion (PN junction 18 which is part of 50, ¶ [0030],[0039]) provided above a semiconductor substrate (e.g. semiconductor body 10’s drain 16 and drift region, ¶ [0033]);
a temperature sensing wiring portion (portions of 15 and 16 connecting 50 to 24 in FIG 1, shown extending in E3-E3 side view of FIG. 5) electrically connected to the temperature sensing portion; and
a protective film (41,42,43, ¶ [0045]) including a temperature sensing protective film (43) provided above the temperature sensing portion (18) and a first wiring protective film (43) provided above the temperature sensing wiring portion, wherein the first wiring protective film (43) includes:
a first region (region above 50) adjacent to the temperature sensing protective film; and
a second region (region between 50 and 24, see Examiner-annotated figure below) provided more spaced apart from the temperature sensing protective film than the first region and having a width narrower than that of the first region (as pictured).
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Regarding claim 4, Meiser discloses the semiconductor device according to claim 1, and Meiser further discloses wherein the first wiring protective film (43) has a stepped shape in a top view (single step from first region to second region, see Examiner-annotated figure above).
Regarding claim 7, Meiser discloses the semiconductor device according to claim 1, and Meiser further discloses wherein the protective film (41,42,43) includes a second wiring protective film (41) extending from the temperature sensing protective film (43) in a direction (into/out of the page of FIG. 4) different from an extending direction of the first wiring protective film (i.e. left/right direction of FIG 4).
Regarding claim 10, Meiser discloses the semiconductor device according to claim 1, and Meiser further discloses wherein the temperature sensing portion (50) is provided at a center of the semiconductor substrate in a top view (center in FIG. 4).
Regarding claim 11, Meiser discloses the semiconductor device according to claim 10, and Meiser further discloses a temperature sensing pad (24, ¶ [0046]) electrically connected to the temperature sensing wiring portion (151’,161’) in a peripheral region of the semiconductor substrate.
Regarding claim 12, Meiser discloses the semiconductor device according to claim 1, and Meiser further discloses wherein the temperature sensing wiring portion includes a cathode wiring portion (n-type side of diode 151’,161’ connected to 24) and an anode wiring portion (22(2) connected to p-type 14’).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is rejected under 35 U.S.C. § 103 as being unpatentable over U.S. 2014/0334522 A1 to Meiser et al., “Meiser”, in view of U.S. 2016/0365294 A1 to Mori, “Mori”.
Regarding claim 5, although Meiser anticipates the semiconductor device according to claim 1, Meiser fails to clearly state wherein a width of the second region (temperature sensor region width) is equal to or greater than 5 µm and equal to or smaller than 500 µm.
Mori teaches incorporating a temperature sensing diode (TD(R)) within the power MOSFET such that the areal occupancy of the conventional prior art is about 83 μm wide and 93 μm long (¶ [0083]) but also teaches reducing the areal occupancy to 10 µm wide and 3 µm long (¶ [0085]), both of which fall within the claimed range.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Meiser with the dimensions of the width of the temperature sensing diode within the claimed range as taught by Mori since the width dimensions were either known in the art (Mori ¶ [0083]) or when reduced would improve the heat response time of the temperature diode (Mori ¶ [0085]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the width determines the distance to the MOSFET and therefore the temperature response time making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claim 6 is rejected under 35 U.S.C. § 103 as being unpatentable over U.S. 2014/0334522 A1 to Meiser et al., “Meiser”, in view of U.S. 2020/0194429 to Naito, “Naito”.
Regarding claim 6, although Meiser anticipates the semiconductor device according to claim 1, Meiser fails to clearly state wherein a length of the second region in an extending direction of the temperature sensing wiring portion is equal to or greater than 500 µm and equal to or smaller than 5000 µm. Meiser shows the length to the half the length of the MOSFET in order to place the temperature diode within the center.
Naito teaches (e.g. FIG. 1A) a temperature diode (90, ¶ [0102]) within the center of the semiconductor device (100) and teaches (e.g. FIG. 2) wherein the length (Wh) of the device may be 3000 μm or greater and 3600 μm or less e.g. 3100 μm (¶ [0134]) and 3100/2 = 1550 μm which falls within the claimed range.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Meiser with the length within the claimed range as suggested by the dimensions of Naito since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the dimensions of the device determine the operating characteristics such as operating voltages making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Allowable Subject Matter
Claim 20 is allowed.
Claims 2-3,8-9,13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art e.g. U.S. Patent Number 6,750,546 B1 to Villaneuva et al. discloses a lead frame (e.g. Figur 3A, Figure 3B) comprising a bonding surface bonded to a semiconductor device (322) via a solder portion, wherein the bonding surface includes: a main surface portion (327) for being bonded (via solder 324) to the semiconductor device (322); and a concave portion (330) provided at an end portion (lip 338) of the main surface portion, as discussed previously.
However, prior art fails to reasonably teach or suggest wherein the lead frame includes a chip connecting portion having a first end side and a second end side opposite to the first end side, wherein the concave portion is provided at the second end side of the chip connecting portion; and wherein, when the lead frame is bonded to a semiconductor device including a first wiring protective film having a first region and a second region narrower than the first region, the concave portion overlaps, in plan view, the second region of the first wiring protective film, together with all of the other limitations of amended claim 20.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. 2023/0430454 A1 to OSAWA teaches (e.g. Fig. 1) a narrowed wiring portion (between 13D and 40P) connecting to a temperature sensing diode (40P, ¶ [0034]).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891
Prosecution Insights