DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-9 are pending in this office action and presented for examination. Claims 1 and 5-6 are newly amended by the response received June 30, 2025.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 5 recites the limitation “the state parameter includes the first state parameter and the second state parameter” in line 4. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0027]) does not appear to provide support for a state parameter that includes two state parameters. For additional discussion regarding this rejection, see the response to arguments below.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation “the arithmetic logic unit coupled to the third multiplexer and the fourth multiplexer and configured to perform an arithmetic logic operation corresponding to the first reduction operation and the second reduction operation on the first input source and the second input source to generate a lane output” in lines 16-19. However, there is insufficient antecedent basis for this limitation in the claims. Examiner notes that while an arithmetic logic unit was previously recited in claim 1, claim 1 did not recite that the arithmetic logic unit was coupled to the third multiplexer and the fourth multiplexer and configured to perform an arithmetic logic operation corresponding to the first reduction operation and the second reduction operation on the first input source and the second input source to generate a lane output. Examiner also notes that claim 1 recited that the aforementioned ALU was included within the lane. For the purposes of this office action, Examiner is interpreting this limitation as “the arithmetic logic unit, wherein the arithmetic logic unit is coupled to the third multiplexer and the fourth multiplexer and is configured to perform an arithmetic logic operation corresponding to the first reduction operation and the second reduction operation on the first input source and the second input source to generate a lane output”. Note that the limitation “the arithmetic unit” is also recited in claim 5, line 25.
Claim 6 recites the limitation “the second operand sub-element” in line 8. However, there is insufficient antecedent basis for this limitation in the claim. For the purposes of this office action, Examiner is interpreting this limitation as “the second operand sub-elements”.
Claim 6 recites the limitation “performing a second reduction operation on a first part and a second part of the first reduction result” in lines 12-13. However, it is indefinite as to whether the limitation “of the first reduction result” further limits just “a second part”, or both “a first part” and “a second part”. For the purposes of this office action, Examiner is taking the latter possibility to be the case, in view of the analogous portion of claim 1.
Claims 7-9 are rejected for failing to alleviate the rejections of claim 6 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 6-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (Lee) (US 20130311530 A1) in view of Ingle et al. (Ingle) (US 20150052330 A1).
Consider claim 1, Lee discloses a vector processor ([0007], line 9, processor; [0007], line 20, vector), comprising: a vector register file (FIG. 12, vector registers 1210; [0150], line 10, register file); and a lane (FIG. 9) coupled to the vector register file (FIG. 9, Input Register v2, Input Register v3, Output Register v1) for loading a first operand (FIG. 9, Input Register v2) and a second operand (FIG. 9, Input Register v3), wherein the first operand (FIG. 9, Input Register v2) includes a first operand element ([0082], line 3, vector element) including a first operand sub-element ([0007], lines 13-19, for example, the bits in a 256-bit register may be specified as a source operand to be operated on as four separate 64-bit packed data elements (quad-word (Q) size data elements), eight separate 32-bit packed data elements (double word (D) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements); in other words, an operand sub-element corresponds to one or more bits that make up the operand element), and the second operand (FIG. 9, Input Register v3) includes a second operand element ([0082], line 3, vector element) including a plurality of second operand sub-elements ([0007], lines 13-19, for example, the bits in a 256-bit register may be specified as a source operand to be operated on as four separate 64-bit packed data elements (quad-word (Q) size data elements), eight separate 32-bit packed data elements (double word (D) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements); in other words, an operand sub-element corresponds to one or more bits that make up the operand element), wherein the lane includes an arithmetic logic unit (ALU) (FIG. 9, Reduction Logic 920; [0082], lines 1-3, the reduction logic unit 920 can perform sum, product, bit-wise or, bit-wise and, bit wise xor, etc., communicative operations) and is configured to select the first operand sub-element as a first input source coupled to the ALU and the second operand sub-elements as a second input source coupled to the ALU ([0092], lines 1-4, Register index field 1044--its content, directly or through address generation, specifies the locations of the source and destination operands, be they in registers or in memory) based on a first state parameter (FIG. 9, output of SR FF 951; [0083], lines 9-10, thus, prior to the first 1, mux 908 provides an input register 901 value to the reduction logic), and wherein the lane performs a first reduction operation (FIG. 9, Reduction Logic 920; [0082], lines 1-3, the reduction logic unit 920 can perform sum, product, bit-wise or, bit-wise and, bit wise xor, etc., communicative operations) on the first input source (FIG. 9, Input Register v2) and the second input source (FIG. 9, Input Register v3) to generate a first reduction result (FIG. 9, output of Reduction Logic 920), and the lane performs a second reduction operation (FIG. 9, Reduction Logic 920; [0082], lines 1-3, the reduction logic unit 920 can perform sum, product, bit-wise or, bit-wise and, bit wise xor, etc., communicative operations) on a first part of the first reduction result and a second part of the first reduction result (FIG. 9, Reduction Logic 920 result being output through Tmp Reg 911 and mux 908 back to Reduction Logic 920) based on a second state parameter (FIG. 9, output of SR FF 951; [0083], lines 10-11, after the first one, it provides a value from a temporary register 911) to generate a second reduction result (FIG. 9, output of Reduction Logic 920).
To any extent to which it may be argued that Lee does not disclose sub-elements, Ingle explicitly discloses sub-elements ([0044], lines 1-3, each input element of the plurality of input elements and each output element of the plurality of output elements may include one or more sub-elements) in the vector reduction context (see FIG. 3, for example). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ingle with the invention of Lee to increase parallelism. Alternatively, this modification merely entails combining prior art elements (the prior art elements of Lee as cited above, and Ingle’s teaching of sub-elements) according to known methods (Ingle teaches implementing sub-elements in the same environment as Lee, as cited above) to yield predictable results (the invention of Lee, implementing sub-elements), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 2, the overall combination entails the vector processor of claim 1 (see above), wherein the second reduction result has a same bit length as the first reduction result (Lee, [0007], lines 13-19, for example, the bits in a 256-bit register may be specified as a source operand to be operated on as four separate 64-bit packed data elements (quad-word (Q) size data elements), eight separate 32-bit packed data elements (double word (D) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements); [0082], lines 1-3, the reduction logic unit 920 can perform sum, product, bit-wise or, bit-wise and, bit wise xor, etc., communicative operations).
Consider claim 3, the overall combination entails the vector processor of claim 1 (see above), wherein the second reduction operation comprises: determining a number of iterations (Lee, for example, [0071], line 5, each iteration of the loop; [0081], lines 6-9, FIG. 9 assumes a sequential implementation (i.e., for N elements, it will take N cycles to complete). The reduction logic unit 920 of this embodiment operates on one element per cycle) for performing arithmetic logic operations (Lee, FIG. 9, Reduction Logic 920; [0082], lines 1-3, the reduction logic unit 920 can perform sum, product, bit-wise or, bit-wise and, bit wise xor, etc., communicative operations) on a plurality of even-numbered parts and a plurality of odd-numbered parts in the first reduction result (Lee, FIG. 9, output of Reduction Logic 920) based on a sub-element length (Ingle, [0044], lines 1-3, each input element of the plurality of input elements and each output element of the plurality of output elements may include one or more sub-elements) and an element length (Lee, [0087], lines 1-17, while embodiments of the invention will be described in which the vector friendly instruction format supports the following: a 64 byte vector operand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) data element widths (or sizes) (and thus, a 64 byte vector consists of either 16 doubleword-size elements or alternatively, 8 quadword-size elements); a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit (1 byte) data element widths (or sizes); a 32 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); and a 16 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); alternative embodiments may support more, less and/or different vector operand sizes (e.g., 256 byte vector operands) with more, less, or different data element widths (e.g., 128 bit (16 byte) data element widths).) to generate the second reduction result (FIG. 9, output of Reduction Logic 920).
Consider claim 4, the overall combination entails the vector processor of claim 1 (see above), wherein the second reduction operation comprises: performing arithmetic logic operations (Lee, FIG. 9, Reduction Logic 920; [0082], lines 1-3, the reduction logic unit 920 can perform sum, product, bit-wise or, bit-wise and, bit wise xor, etc., communicative operations) on a plurality of even-numbered parts and a plurality of odd-numbered parts in the first reduction result (Lee, FIG. 9, output of Reduction Logic 920) based on a sub-element length (Ingle, [0044], lines 1-3, each input element of the plurality of input elements and each output element of the plurality of output elements may include one or more sub-elements) and an element length (Lee, [0087], lines 1-17, while embodiments of the invention will be described in which the vector friendly instruction format supports the following: a 64 byte vector operand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) data element widths (or sizes) (and thus, a 64 byte vector consists of either 16 doubleword-size elements or alternatively, 8 quadword-size elements); a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit (1 byte) data element widths (or sizes); a 32 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); and a 16 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); alternative embodiments may support more, less and/or different vector operand sizes (e.g., 256 byte vector operands) with more, less, or different data element widths (e.g., 128 bit (16 byte) data element widths).) to generate the second reduction result (FIG. 9, output of Reduction Logic 920) within one cycle ([0081], lines 8-11, the reduction logic unit 920 of this embodiment operates on one element per cycle. It should be noted, however, that other embodiments may employ a single cycle operation).
Consider claim 6, Lee discloses an element reduction method ([0081], lines 5-6, a reduction logic unit 920 used to perform reduction in a single operation cycle for N vector elements), comprising: loading a first operand (FIG. 9, Input Register v2) and a second operand (FIG. 9, Input Register v3) based on a first state parameter (FIG. 9, output of SR FF 951; [0083], lines 9-10, thus, prior to the first 1, mux 908 provides an input register 901 value to the reduction logic), wherein the first operand (FIG. 9, Input Register v2) includes a first operand element ([0082], line 3, vector element) including a first operand sub-element ([0007], lines 13-19, for example, the bits in a 256-bit register may be specified as a source operand to be operated on as four separate 64-bit packed data elements (quad-word (Q) size data elements), eight separate 32-bit packed data elements (double word (D) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements); in other words, an operand sub-element corresponds to one or more bits that make up the operand element), and the second operand (FIG. 9, Input Register v3) includes a second operand element ([0082], line 3, vector element) including a plurality of second operand sub-elements ([0007], lines 13-19, for example, the bits in a 256-bit register may be specified as a source operand to be operated on as four separate 64-bit packed data elements (quad-word (Q) size data elements), eight separate 32-bit packed data elements (double word (D) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements); in other words, an operand sub-element corresponds to one or more bits that make up the operand element); selecting the first operand sub-element as a first input source coupled to an arithmetic logic unit (ALU) (FIG. 9, Reduction Logic 920; [0082], lines 1-3, the reduction logic unit 920 can perform sum, product, bit-wise or, bit-wise and, bit wise xor, etc., communicative operations) and the second operand sub-element as a second input source coupled to the ALU ([0092], lines 1-4, Register index field 1044--its content, directly or through address generation, specifies the locations of the source and destination operands, be they in registers or in memory) based on the first state parameter (FIG. 9, output of SR FF 951; [0083], lines 9-10, thus, prior to the first 1, mux 908 provides an input register 901 value to the reduction logic); performing a first reduction operation (FIG. 9, Reduction Logic 920; [0082], lines 1-3, the reduction logic unit 920 can perform sum, product, bit-wise or, bit-wise and, bit wise xor, etc., communicative operations) on the first input source (FIG. 9, Input Register v2) and the second input source (FIG. 9, Input Register v3) to generate a first reduction result (FIG. 9, output of Reduction Logic 920); and performing a second reduction operation (FIG. 9, Reduction Logic 920; [0082], lines 1-3, the reduction logic unit 920 can perform sum, product, bit-wise or, bit-wise and, bit wise xor, etc., communicative operations) on a first part and a second part of the first reduction result (FIG. 9, Reduction Logic 920 result being output through Tmp Reg 911 and mux 908 back to Reduction Logic 920) based on a second state parameter (FIG. 9, output of SR FF 951; [0083], lines 10-11, after the first one, it provides a value from a temporary register 911) to generate a second reduction result (FIG. 9, output of Reduction Logic 920).
To any extent to which it may be argued that Lee does not disclose sub-elements, Ingle explicitly discloses sub-elements ([0044], lines 1-3, each input element of the plurality of input elements and each output element of the plurality of output elements may include one or more sub-elements) in the vector reduction context (see FIG. 3, for example). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Ingle with the invention of Lee to increase parallelism. Alternatively, this modification merely entails combining prior art elements (the prior art elements of Lee as cited above, and Ingle’s teaching of sub-elements) according to known methods (Ingle teaches implementing sub-elements in the same environment as Lee, as cited above) to yield predictable results (the invention of Lee, implementing sub-elements), which is an example of a rationale that may support a conclusion of obviousness as per MPEP 2143.
Consider claim 7, the overall combination entails the element reduction method of claim 6 (see above), wherein the second reduction result has a same bit length as the first reduction result (Lee, [0007], lines 13-19, for example, the bits in a 256-bit register may be specified as a source operand to be operated on as four separate 64-bit packed data elements (quad-word (Q) size data elements), eight separate 32-bit packed data elements (double word (D) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements); [0082], lines 1-3, the reduction logic unit 920 can perform sum, product, bit-wise or, bit-wise and, bit wise xor, etc., communicative operations).
Consider claim 8, the overall combination entails the element reduction method of claim 6 (see above), wherein the second reduction operation comprises: determining a number of iterations (Lee, for example, [0071], line 5, each iteration of the loop; [0081], lines 6-9, FIG. 9 assumes a sequential implementation (i.e., for N elements, it will take N cycles to complete). The reduction logic unit 920 of this embodiment operates on one element per cycle) for performing arithmetic logic operations (Lee, FIG. 9, Reduction Logic 920; [0082], lines 1-3, the reduction logic unit 920 can perform sum, product, bit-wise or, bit-wise and, bit wise xor, etc., communicative operations) on a plurality of even-numbered parts and a plurality of odd-numbered parts in the first reduction result (Lee, FIG. 9, output of Reduction Logic 920) based on a sub-element length (Ingle, [0044], lines 1-3, each input element of the plurality of input elements and each output element of the plurality of output elements may include one or more sub-elements) and an element length (Lee, [0087], lines 1-17, while embodiments of the invention will be described in which the vector friendly instruction format supports the following: a 64 byte vector operand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) data element widths (or sizes) (and thus, a 64 byte vector consists of either 16 doubleword-size elements or alternatively, 8 quadword-size elements); a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit (1 byte) data element widths (or sizes); a 32 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); and a 16 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); alternative embodiments may support more, less and/or different vector operand sizes (e.g., 256 byte vector operands) with more, less, or different data element widths (e.g., 128 bit (16 byte) data element widths).) to generate the second reduction result (FIG. 9, output of Reduction Logic 920).
Consider claim 9, the overall combination entails the element reduction method of claim 6 (see above), wherein the second reduction operation comprises: performing arithmetic logic operations (Lee, FIG. 9, Reduction Logic 920; [0082], lines 1-3, the reduction logic unit 920 can perform sum, product, bit-wise or, bit-wise and, bit wise xor, etc., communicative operations) on a plurality of even-numbered parts and a plurality of odd-numbered parts in the first reduction result (Lee, FIG. 9, output of Reduction Logic 920) based on a sub-element length (Ingle, [0044], lines 1-3, each input element of the plurality of input elements and each output element of the plurality of output elements may include one or more sub-elements) and an element length (Lee, [0087], lines 1-17, while embodiments of the invention will be described in which the vector friendly instruction format supports the following: a 64 byte vector operand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) data element widths (or sizes) (and thus, a 64 byte vector consists of either 16 doubleword-size elements or alternatively, 8 quadword-size elements); a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit (1 byte) data element widths (or sizes); a 32 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); and a 16 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); alternative embodiments may support more, less and/or different vector operand sizes (e.g., 256 byte vector operands) with more, less, or different data element widths (e.g., 128 bit (16 byte) data element widths).) to generate the second reduction result (FIG. 9, output of Reduction Logic 920) within one cycle ([0081], lines 8-11, the reduction logic unit 920 of this embodiment operates on one element per cycle. It should be noted, however, that other embodiments may employ a single cycle operation).
Response to Arguments
Applicant on page 6 argues: “Claims 1, 5, and 6 are amended to clearly define the claimed invention. Please see supporting ground in the discussion of 35 U.S.C. 112(a) and 35 U.S.C. 112(b). The applicant respectfully submits that the amendment is supported by at least the paragraphs cited below.”
Examiner again thanks Applicant for his time and effort in providing detailed explanations and citations to the specification throughout the remarks.
Applicant on page 7 argues: “Paragraph [0038] is amended as above to make the sentence easier to understand.”
In view of the aforementioned amendment, the previously presented objections to the specification are withdrawn.
Applicant across pages 7-15 argues that the amendments and/or arguments overcome the previously presented rejections.
In view of the aforementioned amendments and/or arguments, most of the previously presented rejections are withdrawn; see below for responses to arguments for the rejections that appear to remain applicable.
Applicant on page 7 argues: ‘Regarding to item 7 of the Office action, the Office indicated that "the original disclosure does not appear to provide support for the limitation of "the state parameter includes the first state parameter and the second state parameter". The applicant respectfully disagrees. Paragraph [0027] of the as-filed specification, as well as paragraph [0053] (which the application is directed to), teaches "the FSM of the element reduction operation includes an Idle Complete State 801, an Initial State 802, and a Sub-elements Reduction State 803, and each state corresponds to a different state parameter STATE". The applicant respectfully submits that the as-filed specification clearly defines and supports that different values of the state parameter refer to different state parameters. Based on the above, the applicant respectfully submits that the pending claims are fully supported and described in the as-filed specification.’
However, Applicant’s citation and argument do not appear to convey that there is a state parameter that includes a first state parameter and a second state parameter. For example, FIG. 8 does not show an oval that compasses two (or three) of 801, 802, and 803. In addition, to any extent that the original disclosure provides support for a parameter “STATE” that can be assigned one of three different values (respectively corresponding to Idle/Complete State 801, Initial State 802, and Sub-elements Reduction State 803) to reflect the current state, Examiner submits that such behavior is not synonymous with a state parameter “including” a first state parameter and a second state parameter. Examiner recommends reciting language akin to “based on whether a state parameter is the first state parameter or the second state parameter” rather than “based on a state parameter, wherein the state parameter includes the first state parameter and the second state parameter”.
Applicant on page 11 argues: ‘Regarding to item 16 of the Office action, the Office asserted that "the limitation 'the arithmetic logic unit coupled to the third multiplexer and the fourth multiplexer and configured to perform an arithmetic logic operation on the first input source and the second input source to generate a lane output'in lines 16-18". The applicant has corrected the typographical error of ALU previously recited in claim 1, and thus the rejection should be moot.’
However, Examiner notes that the aforementioned rejection was not based on the typographical error of ALU and appears to remain applicable. Examiner also notes that while an arithmetic logic unit was previously recited in claim 1, claim 1 did not recite that the arithmetic logic unit was coupled to the third multiplexer and the fourth multiplexer and configured to perform an arithmetic logic operation corresponding to the first reduction operation and the second reduction operation on the first input source and the second input source to generate a lane output. Examiner also notes that claim 1 recited that the aforementioned ALU was included within the lane. For the purposes of this office action, Examiner is interpreting this limitation as “the arithmetic logic unit, wherein the arithmetic logic unit is coupled to the third multiplexer and the fourth multiplexer and is configured to perform an arithmetic logic operation corresponding to the first reduction operation and the second reduction operation on the first input source and the second input source to generate a lane output”.
Applicant on page 15 argues: “Regarding to items 21-24, please the remark for claim 1.”
Examiner notes that that the rejection set forth in paragraph 23 of the previous office action appears to remain applicable, in view of claim 6 reciting “the second operand sub-element” at a location where claim 1, in an analogous location, recites “the second operand sub-elements”. Examiner also notes that that the rejection set forth in paragraph 24 of the previous office action appears to remain applicable, and does not appear to have a corresponding remark associated with claim 1, as this rejection was specific to claim 6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fleischer et al. (US 20140047214 A1) discloses sub-elements ([0040], lines 6-7, For example, the VCR 414 can include 16 vector register entries with 32 elements each of 64 bits; [0040], lines 10-20, a variable number of execution slots can be used, operating on an equal number of sub-elements, whereby the sub-elements taken together add up to one register element (either VCR 414 or SCR 416) of 64 bits in this example. The number of execution slots and the corresponding number of vector sub-elements depend upon the data type of the instruction. Examples of data types and sizes of various formats include: floating-point with double-precision (64-bit) and single-precision (32-bit) data types and fixed-point for a doubleword (64-bit), word (32-bit), halfword (16-bit), and byte (8-bit) data types), which is relevant to the claimed sub-elements.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2182