DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 12/30/2024 has been considered.
Drawings
The drawings filed on 02/21/2024 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 02/21/2024 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10, 11 and 13 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Huang (US 2023/0337426).
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Regarding claim 1, Huang (US 2023/0337426) discloses:
A memory device, comprising:
a substrate (¶0030 discloses layer 50 is disposed above an interconnect layer connected to a die on a substrate);
an interconnect located above the substrate (¶0030 discloses substrate 50 is over an interconnect layer connected to a die on a substrate);
a first stop pad (24, ¶0040) and a second stop pad (24, ¶0040) located above the interconnect;
a stacked structure (gate stack structure GSK, ¶0031), located above the substrate the first stop pad (52) and the second stop pad (52);
a channel pillar (16, ¶0030), extending through the stacked structure (GSK);
a charge storage structure (40, ¶0030), located between the channel pillar (16) and the stacked structure (GSK);
a first conductive pillar (32a, ¶0030) and a second conductive pillar (32b, ¶0030), located in the channel pillar (16) and coupled to the channel pillar (16), wherein the first conductive pillar lands on the first stop pad (24), and the second conductive pillar (32b) lands on the second stop pad (24); and
a first conductive plug (31a, ¶0038), located between the interconnect ( below layer 50, ¶0030) and the first stop pad (24), wherein the first conductive pillar (32a) is electrically connected to a first device on the substrate through the first conductive plug (31a), the first stop pad (24), and the interconnect (¶0030).
Regarding claim 10, Huang further discloses:
wherein a top surface of the first conductive pillar (32a, 132 in figure 6=3H) is completely covered by a dielectric layer (115, ¶0066), and no conductive plug lands on the top surface of the first conductive pillar.
Regarding claim 11, Huang discloses:
A memory device, comprising:
a substrate (¶0030);
an interconnect, located above the substrate (¶0030);
a plurality of first stop pads (24) and a plurality of second stop pads (24), located above the interconnect;
a stacked structure (GSK), located above the first stop pads (24) and the second stop pads (24);
a plurality of channel pillars (16), extending through the stacked structure and arranged in two adjacent rows (¶0024);
a plurality of pairs of conductive pillars (32a, 32b), wherein each of the pairs of the conductive pillars is disposed in one of the channel pillars (16), a first conductive pillar (32a) of the each of the pairs of the conductive pillars lands on one of the first stop pads (24), and a second conductive pillar (32b) of the each of the pairs of the conductive pillars lands on one of the second stop pads (24); and
a plurality of first conductive plugs (31a), located between the interconnect (and the first stop pads (24), wherein each of the first conductive pillars (32a) is electrically connected to a first device on the substrate through a corresponding first conductive plug (31a) of the first conductive plugs, a corresponding first stop pad (24) of the first stop pads, and the interconnect (¶0030), wherein the second conductive pillars are adjacent to each other and are located between the first conductive pillars (¶0024).
Regarding claim 13, Huang further discloses:
wherein in the channel pillars arranged in the two adjacent rows, each of the pairs of the conductive pillars in a first row of the two adjacent rows is arranged along a first direction, each of the pairs of the conductive pillars in a second row of the two adjacent rows is arranged along a second direction, and the first direction is different from the second direction (figure 1b).
Allowable Subject Matter
Claims 2-9, 12 and 14-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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/WILLIAM A HARRISTON/ Primary Examiner, Art Unit 2899
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