Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I, Species A (Fig. 4, claims 1-19) in the reply filed on 04/28/2026 is acknowledged.
Claim 20 has been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/28/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/20/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi (US 2022/0102372).
As for claim 1, Choi discloses in Figs. 1-15B and the related text a memory device comprising:
a stacked structure ST comprising a plurality of first insulating layers 12 and a plurality of first conductive layers 11 stacked alternately (FIG. 1);
a second conductive layer 13 over the stacked structure ST;
a plurality of channel pillars CH extending through the second conductive layer and the stacked structure (FIG 1), wherein each of the plurality of channel pillars comprises:
a first portion CH1/CH3 extending through the stacked structure (FIG. 1); and
a second portion CP/CH2 on the first portion and extending through the second conductive layer (FIG. 1), wherein a diameter of (upper portion of) the first portion is greater than a diameter of (lower portion of) the second portion (FIG. 3);
a plurality of charge storage structures 16, surrounding the plurality of channel pillars CH and in contact with the second conductive layer 13 (FIG. 2C); and
a string selection line cut slit SLS extending through the second conductive layer 13 and disposed between the second portions CP/CH2 of two adjacent channel pillars among the plurality of channel pillars (FIG. 1).
As for claim 2, Choi discloses the memory device according to claim 1, further comprising a substrate 10 underlying the stacked structure ST (FIG. 1). .
As for claim 3, Choi discloses the memory device according to claim 1, wherein a second distance between the second portions CP/CH2 of two adjacent channel pillars is greater than a first distance between the first portions CH1/CH3 of the two adjacent channel pillars (FIG. 1).
As for claim 4, Choi discloses the memory device according to claim 3, wherein a third distance between the string selection line cut slit SLS and a second portion CP/CH2 of a neighboring channel pillar is smaller than the second distance (FIG 1).
As for claim 5, Choi discloses the memory device according to claim 1, wherein a region between the string selection line cut slit SLS and a second portion CP/CH2 of a neighboring channel pillar is free of a dummy pillar (FIG. 1).
As for claim 6, Choi discloses the memory device according to claim 3, further comprising a separation wall 24 extending through the second conductive layer 13 and the stacked structure ST, wherein a fourth distance between the separation wall 24 and a second portion CP/CH2 of another channel pillar is greater than (a portion of) the third distance (FIG. 1).
As for claim 7, Choi discloses the memory device according to claim 1, wherein a sidewall of the string selection line cut slit SLS is in contact with the second conductive layer 13 (FIG. 1).
As for claim 8, Choi discloses the memory device according to claim 1, wherein the string selection line cut slit SLS does not extend beyond a topmost first conductive layer 13 of the stacked structure (FIG. 1).
As for claim 9, Choi discloses the memory device according to claim 1, wherein a thickness of the second conductive layer 13 is greater than a thickness of each of the plurality of first conductive layers 11 (FIG. 1).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 10-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Iwai (US 10,290,650).
As for claim 10, Choi discloses the memory device according to claim 1, wherein the second portion CP/CH2 comprises:
a conductive cap CP;
a second insulating layer 26 located below the conductive cap (FIG. 1); and
a channel layer 25 located between the charge storage structure 16 and the second insulating layer 26, wherein the charge storage structure 16 surrounds (a portion of) the channel layer 25, the second insulating layer 26, and the conductive cap and is in contact with the second conductive layer 13 (FIG 1).
Choi does not disclose the charge storage structure surrounds the conductive cap.
Iwai teaches in Fig. 15D and the related text a charge storage structure 50 surrounds the conductive cap 63.
Choi and Iwai are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Choi because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Choi to include the limitations as taught by Iwai in order to improve performance of the memory device.
As for claim 11, Choi discloses the memory device according to claim 10, wherein a width of (any portion of) the string selection line cut slit SLS is smaller than twice a thickness of the charge storage structure 16 (FIG. 1).
As for claim 13, Choi discloses the memory device according to claim 10, wherein the first portion comprises an air gap 17 surrounded by the second insulating layer 26, and the second portion CP/CH2 is free of an air gap 17 (FIG 1).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Iwai and further in view of Du et al. (US 2023/0071503).
As for claim 12, Choi discloses the memory device according to claim 10, wherein the string selection line cut slit SLS is free of a channel layer (FIG. 1).
Choi does not disclose the string selection line cut slit comprises the charge storage structure.
Du et al. teach in Fig. 16 and the related text a string selection line cut slit 124 comprises the charge storage structure [0149].
Choi, Iwai and Du et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by Du et al., in order to carry out more precise control for memory strings of the sub-areas (Du et al.: [0150])
Claims 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Zhang et al. (US 2024/0224520).
As for claim 14, Choi discloses the memory device according to claim 1, except the string selection line cut slit has a wavy shape in a top view.
Zhang et al. teach in Fig. 12B and the related text a string selection line cut slit 350 has a wavy shape in a top view [0138].
Choi and Zhang et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Choi because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Choi to include the limitations as taught by Zhang et al., in order to achieve the device properties.
As for claim 15, Choi discloses in Figs. 1-15B and the related text a memory device comprising:
a stacked structure ST comprising a plurality of insulating layers 12 and a plurality of first conductive layers 11 stacked alternately (FIG. 1);
a second conductive layer 13 on the stacked structure;
a string selection line cut slit SLS extending through the second conductive layer 13 (FIG. 1);
a plurality of first channel pillars CH1/CH3 extending through the second conductive layer and the stacked structure in a first sub-zone (FIG. 1); and
a plurality of second channel pillars CH1 extending through the second conductive layer 13 and the stacked structure in a second sub-zone (FIG. 1),
wherein the string selection line cut slit SLS/21 is arranged between the plurality of first channel pillars and the plurality of second channel pillars (FIG. 1), wherein the string selection line cut slit SLS/21 divides the second conductive layer into a first sub-zone and a second sub-zone (FIG. 1).
Choi does not disclose the second conductive layer between the stacked structure and an interconnect layer having a plurality of conductive plugs; and the string selection line cut slit has a wavy shape and divides the second conductive layer into a first sub-zone and a second sub-zone.
Zhang et al. teach in Fig. 12A-13 second conductive layer 330/150 between the stacked structure and an interconnect layer 175/192 having a plurality of conductive plugs 175/192; and the string selection line cut slit 350 has a wavy shape [0138] and divides the second conductive layer 330 into a first sub-zone and a second sub-zone (Fig. 13).
Choi and Zhang et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Choi because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Choi to include the limitations as taught by Zhang et al., in order to provide interconnections and achieve the device properties.
As for claim 16, Choi discloses the memory device according to claim 15, wherein the string selection line cut slit 21 does not extend beyond a topmost first conductive layer 13 of the stacked structure (Fig. 1).
As for claim 17, Choi discloses the memory device according to claim 15, further comprising a separation wall 24 extending through the second conductive layer 13 and (a portion of) the stacked structure ST, wherein the separation wall 24 has a strip shape (FIG. 2A)
Choi in view of Zhang et al. teach the strip shape different from the wavy shape of the string selection line cut slit.
As for claim 18, Choi discloses the memory device according to claim 15, wherein an interface region between the first sub-zone region and the second sub-zone region is free of a dummy pillar (Fig. 1).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Zhang et al. and further in view of Du et al.
As for claim 19, Choi discloses the memory device according to claim 15, except wherein the string selection line cut slit is conformal with partial sidewalls of the plurality of first channel pillars and partial sidewalls of the plurality of second channel pillars .
Du et al. teaches in Fig. 16 and the related text a string selection line cut slit 124 is conformal with partial sidewalls of the plurality of first channel pillars (left 139) and partial sidewalls of the plurality of second channel pillars (right 139).
Choi, Zhang and Du et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the combined device because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the combined device to include the limitations as taught by Iwai in order to provide lateral separation (Iwai: col. 11 lines 35-40).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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