Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
All references cited on the previously mailed Notice[s] of References Cited (PTO-892) have been reviewed. The arguments and amendments presented in the response filed on 7/31/2025, in combination with the examiner's review of all prior art of record, have led to the conclusion that the claims are now allowable.
Response to Arguments
Applicant’s arguments with respect to the newly amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ozeki et al. (US 20220328531 A1) in view of Lee et al. (US 20220189939 A1).
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CLAIM 1. Ozeki teaches a display device, comprising:
a substrate SUB having a peripheral region (Ozeki - Fig. 1A); and
a circuit disposed on the peripheral region (peripheral circuit region) and comprising a plurality of transistors (Tr2-1, Tr2-2), wherein one of the plurality of transistors comprises:
a semiconductor layer S comprising a channel region S1 extending in a longitudinal direction in a top view;
a first electrode disposed at a side of the channel region and comprising a first portion W2 (i.e. electrode on left side); and
a second electrode W1 disposed at another side of the channel region (i.e. electrode on right side)and comprising a second portion W1, a width of the first portion of the first electrode is greater than a width of the second portion of the second electrode (Ozeki, Fig. 1A, demonstrates the claimed subject matter in a cross sectional view similar to Applicant’s own figure 6. Figure 1A of Ozeki shows portions of electrodes (W2 and W1) that meet the broadest reasonable interpretation (BRI) of the claim language, specifically depicting a configuration where a portion of W2 is greater in width than a portion of W1. As the claim term “portion” fails to define precise boundaries, the structure shown in Ozeki, Fig. 1A, reads directly on the claim language.).
Ozeki however may be silent upon wherein the first electrode and the second electrode have variable widths changing along the longitudinal direction in the top view in a horizontal direction in the top view, as the top plan view of Ozeki may not clearly show the shapes of the relevant portions of the electrodes. While Ozeki discloses the overall Thin-Film Transistor (TFT) structure and vertical contact configuration (substrate, channel, source/drain via plugs/electrodes), its top-plan view may obscure the precise shapes of the relevant electrode portions.
Lee demonstrates that patterning interconnect and electrode lines with variable widths along their length, such as widened pad sections versus narrowed trace sections—is routine in the art to accommodate adjacent wiring or spacing constraints. As shown in Lee (e.g., Fig. 2, depicting traces corresponding to the upper portion of W2and/or W1, such trace portions often include jogs or bends, inherently producing variable widths in the longitudinal direction.
A Person Having Ordinary Skill in the Art (PHOSITA) would immediately recognize that the upper trace portion of an electrode for routing is capable of, and routinely designed to possess, this recited shape. Therefore, it would have been obvious to a PHOSITA to design Ozeki’s source/drain electrodes to have variable widths along the longitudinal direction, as taught by Lee. This modification requires no unexpected restructuring and would be implemented in order to optimize routing density, provide sufficient contact pad area over vias and/or maintain proper electrical isolation and spacing with adjacent conductive traces
By substituting this modification into Ozeki, a PHOSITA would have had a high reasonable expectation of success in achieving a reliable and manufacturable TFT layout.
CLAIM 2. Ozeki discloses a display device of claim 1, wherein the circuit comprises a multiplexer circuit or a gate driving circuit (Ozeki ¶108).
CLAIM 3. Ozeki discloses a display device of claim 1, wherein the first electrode is a source or a drain (Ozeki Fig. 1A).
CLAIM 4. Ozeki discloses a display device of claim 1, wherein the second electrode is a source or a drain (Ozeki Fig. 1A).
CLAIM 5. Ozeki discloses a display device of claim 1, wherein the first portion is electrically connected to the semiconductor layer via a hole (Ozeki Fig. 1A).
CLAIM 6. Ozeki discloses a display device of claim 5, further comprising an insulating layer IL1 disposed on the substrate, and the hole WCON penetrates through the insulating layer (Ozeki Fig. 1A).
CLAIM 7. Ozeki discloses a display device of claim 1, wherein the second electrode further comprises a third portion, the third portion is adjacent to the second portion, and the third portion is electrically connected to the semiconductor layer via another hole (Ozeki Fig. 1A - Under the broadest reasonable interpretation (BRI) consistent with the specification, the claim term "portion" is deemed to be a general, non-limiting term referring to a segment or region. Given this interpretation, the structure shown in Ozeki, Fig. 1A, reads directly on the claim language.).
CLAIM 8. Ozeki discloses a display device of claim 7, wherein a width of the third portion is greater than a width of the second portion of the second electrode (Ozeki Fig. 1A - Under the broadest reasonable interpretation (BRI) consistent with the specification, the claim term "portion" is deemed to be a general, non-limiting term referring to a segment or region. Given this interpretation, the structure shown in Ozeki, Fig. 1A, reads directly on the claim language.).
CLAIM 9. Ozeki discloses a display device of claim 7, wherein the first electrode further comprises a fourth portion, the fourth portion is adjacent to the first portion, and the fourth portion is electrically connected to the semiconductor layer via another hole (Ozeki Fig. 1A - Under the broadest reasonable interpretation (BRI) consistent with the specification, the claim term "portion" is deemed to be a general, non-limiting term referring to a segment or region. Given this interpretation, the structure shown in Ozeki, Fig. 1A, reads directly on the claim language.).
CLAIM 10. Ozeki discloses a display device of claim 9, wherein a width of the third portion is greater than a width of the second portion, and a width of the first portion is greater than a width of the fourth portion (Ozeki Fig. 1A - Under the broadest reasonable interpretation (BRI) consistent with the specification, the claim term "portion" is deemed to be a general, non-limiting term referring to a segment or region. Given this interpretation, the structure shown in Ozeki, Fig. 1A, reads directly on the claim language.).
CLAIM 11. Ozeki discloses a display device of claim 1, however may be silent upon wherein the first electrode has a curved outer edge, the outer edge has a first bending angle, and the first bending angle is 100 degrees to 160 degrees. Ozeki teaches, in the plan view of Fig. 2, wiring layers capable of having bending angles in the effective range. While Ozeki may not explicitly dictate a specific angle, the selection of a particular bending angle within the effective range taught by Ozeki is deemed a matter of obvious design choice (or "design need") within the ordinary skill of an artisan, failing to produce any unexpected results or benefits.
The angular adjustment recited in the claim is a simple change of shape, size, or orientation of an article, which constitutes a routine expedient within the skill of an ordinary practitioner to optimize performance (e.g., reducing space) rather than a patentable invention. Therefore, the subject matter as a whole would have been obvious to a person of ordinary skill in the art at the time of the invention.
CLAIM 12. Ozeki discloses a display device of claim 11, further comprising a signal line disposed between adjacent two of the plurality of transistors, and the signal line has a second bending angle, and a difference between the second bending angle and the first bending angle is within 10 degrees (Ozeki Fig. 2 – adjacent signal lines may have the same angles meeting the scope of the claim.)
CLAIM 13. Ozeki discloses a display device of claim 12, wherein a separation distance between an edge of the signal line and the outer edge is substantially maintained constant (Ozeki Fig. 2 – adjacent signal lines may have the same angles meeting the scope of the claim.)
CLAIM 14. Ozeki discloses a display device of claim 1, further comprising a first signal line and a second signal line, wherein the first signal line and the second signal line are disposed between adjacent two of the plurality of transistors, and the first signal line and the second signal line are different layers (Ozeki Figs. 1& 2 – As shown in the figures provided by Ozeki, the wiring is arranged on multiple, overlapping levels. The peripheral driving circuit dictates pixel structure operation in distinct rows via dedicated signal lines, facilitating sequential scanning and independent data writing to ensure accurate image rendering across the entire display region.).
CLAIM 15. The display device of claim 14, further comprising a plurality of pixel structures, wherein the substrate also has a display region adjacent to the peripheral region and the plurality of pixel structures are disposed in the display region, and the first signal line and the second signal line respectively control the plurality of pixel structures in different rows (Ozeki Figs. 1).
CLAIM 16. Ozeki discloses a display device of claim 15, wherein the first signal line and the second signal line are adjacent to each other in a horizontal direction (Ozeki Figs. 1& 2).
CLAIM 17. Ozeki discloses a display device of claim 1, further comprising a signal line, wherein the second electrode of one of the transistors and the second electrode of another of the transistors are commonly connected to the signal line (Ozeki Figs. 1, 2 and 7).
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CLAIM 18. The display device of claim 1, further comprising a control line, wherein both one of the transistors and another transistor are controlled by the control line GL1 (Ozeki Figs. 1, 2, 7 and 11).
CLAIM 19. Ozeki discloses a display device of claim 1, further comprising a connecting line, wherein a gate of one of the transistors is connected to a gate of another transistor via the connecting line GL1 (Ozeki Figs. 1, 2, 7 and 11).
CLAIM 20. Ozeki discloses a display device of claim 1, further comprising a signal line, wherein a gate of one of the transistors and a gate of another transistor are commonly connected to the signal line GL1 (Ozeki Figs. 1, 2, 7, 11 and 17).
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
7/21/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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