DETAILED ACTION
This office action is in response to the preliminary amendment filed 7/15/2024.
Currently, claims 1-20 are pending.
Election/Restrictions
A restriction between the structure as claimed in claims 1-19 and the method claimed in claim 20 is not necessary at this time, as the method merely recites the steps of forming the features that are present in claim 1, and thus there is not a serious burden to examine both the structure and the device as they are currently claimed. However, should the claims be amended in a manner that recites specific method steps that are not necessarily required to fabricate the device as claimed, then a restriction may be required.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 2/21/2024 and 11/13/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 11, 14-17 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cai et al. (US 11,164,881).
Pertaining to claims 1 and 20, Cai shows, with reference to FIG. 1, a structure for a flash memory cell array, the structure comprising:
(forming) a first gate stack (top) including a first control gate (CG), the first control gate having a first sidewall (towards top of page), a second sidewall (towards bottom of page) opposite from the first sidewall, and a first gate strap region (120), the first gate strap region including a first projection (125) extending outwardly from only the first sidewall of the first control gate; and
(forming) a second gate stack (middle) including a second control gate (CG), the second control gate having a first sidewall (towards bottom of page) and a second sidewall (towards top of page) opposite from the first sidewall, and the second sidewall of the second control gate facing the second sidewall of the first control gate.
Pertaining to claim 2, Cai shows the second sidewall of the second control gate is spaced from the second sidewall of the first control gate by a gap of uniform dimension in the first gate strap region (FIG. 1).
Pertaining to claim 3, Cai shows the first projection of the first gate strap region extends away from the second sidewall of the first control gate (FIG. 1).
Pertaining to claim 4, Cai shows the first projection of the first gate strap region does not extend outward from the second sidewall of the first control gate (FIG. 1).
Pertaining to claim 5, Cai shows the second sidewall of the second control gate extends parallel to the second sidewall of the first control gate (FIG. 1).
Pertaining to claim 6, Cai shows the second control gate has a second gate strap region (120), and the second gate strap region includes a second projection extending outwardly from only the first sidewall of the second control gate (FIG. 1).
Pertaining to claim 7, Cai shows the second sidewall of the second control gate is spaced from the second sidewall of the first control gate by a gap of uniform dimension in the first gate strap region and in the second gate strap region (FIG. 1).
Pertaining to claim 8, Cai shows a first contact coupled to the first gate strap region of the first control gate and a second contact coupled to the second gate strap region of the second control gate (FIG. 1; col. 8, lines 62-64).
Pertaining to claim 11, Cai shows the first control gate has a first width dimension in the first gate strap region, the second control gate has the first width dimension in the second gate strap region, the first control gate has a second width dimension outside of the first gate strap region, the second control gate has the second width dimension outside of the second gate strap region, and the first width dimension is greater than the second width dimension (FIG. 1).
Pertaining to claims 14 and 19, Cai shows a first access gate (231/WL) adjacent to the first sidewall of the first control gate, wherein the first access gate terminates at the first gate strap region (FIG. 1-3A).
Pertaining to claim 15, Cai shows a second access gate (221/WL) adjacent to the first sidewall of the second control gate, wherein the second access gate terminates at the second gate strap region (FIG. 1-3A).
Pertaining to claim 16, Cai shows a semiconductor substrate (205), wherein the first gate stack further includes a first floating gate (233) between the first control gate (235) and the semiconductor substrate, and the second gate stack further includes a second floating gate (223) between the second control gate (225) and the semiconductor substrate (FIG. 2).
Pertaining to claim 17, Cai shows the first control gate has a first width dimension in the first gate strap region, the first control gate has a second width dimension outside of the first gate strap region, and the first width dimension is greater than the second width dimension (FIG. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Cai.
Cai shows the structure of claim 6. However, in a different interpretation, region 120 may be interpreted to be only the first gate strap region. In this case, Cai fails to explicitly show the second gate strap region including the second projection extending outwardly from only the first sidewall of the second control gate.
However, Cai does teach that there may be more than one strap region per row of the memory cell array (col. 4, lines 26-27). Applying this teaching to e.g. FIG. 1 would then result in a second gate strap region that, like the first gate strap region, would include the second projection extending outwardly from only the first sidewall of the second control gate.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a second strap region in the array of Cai in the case that it is required for design based on e.g. performance or length of row (col. 4, lines 27-29).
Pertaining to claim 9, Cai shows a first memory cell (140) between the first gate strap region and the second gate strap region, the first memory cell including a first portion of the first gate stack and a first source/drain region (FIG. 1-2). Although Cai does not explicitly show a second memory cell between the first gate strap region and the second gate strap region, the second memory cell including a second portion of the first gate stack and a second source/drain region, Cai does teach in col. 5, lines 23-25 that isolation regions are used to isolate columns of memory cells. Furthermore, Cai shows in FIG. 1 that the region comprising the first memory cell is repeated. Considering these teaching, it would be obvious for a second memory cell to be adjacent the first memory cell (and separated by an isolation region).
Allowable Subject Matter
Claims 10, 12-13 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As it pertains to claim 10, the prior art of record does not teach or suggest a first bit line coupled to the first source/drain region of the first memory cell; and a second bit line coupled to the second source/drain region of the second memory cell, wherein the first bit line and the second bit line are disposed between the first gate strap region and the second gate strap region, and the first bit line and the second bit line extend across the first gate stack and the second gate stack in combination with the limitations recited in the claims on which claim 10 depends.
As it pertains to claims 12-13 and 18, although Cai shows an erase gate (220) between the second sidewall of the first control gate and the second sidewall of the second control gate, there is no teaching or suggestion that the erase gate terminates at the first gate strap region.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shuai et al. (US 2023/0171958), Hsu et al. (US 11,869,951) and Wu et al. (US 11,527,543) disclose structures similar to that disclosed by Applicant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896
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