DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., (Kim) US 2022/0189967 in view of Yoon et al., (Yoon) US 2022/0181457.
Regarding claim 1, Kim shows in FIG. 1-6H, a semiconductor device comprising: a substrate (110) [0032] comprising an element isolation layer (116)[0033] defining a plurality of active areas (117)[0034]; and a plurality of gate structures (120)[0038] intersecting the plurality of active areas (117), wherein each of the plurality of gate structures comprises: a gate insulating layer (122) comprising a first region containing a first material; and a gate electrode layer (120) on the gate insulating layer (122).
Kim differs from the claimed invention because he does not explicitly disclose a device wherein each of the plurality of gate structures comprises: a gate insulating layer comprising a first region containing a first material and a second region containing a second material different from the first material on the active area; wherein a concentration of the second material in the first region is less than a concentration of the second material in the second region, and a thickness of the gate insulating layer in the first region is less than the thickness of the gate insulating layer in the second region.
Yoon discloses and shows in FIG. 17, a device wherein each of the plurality of gate structures comprises: a gate insulating layer comprising a first region (108) containing a first material and a second region (106) containing a second material different from the first material on the active area; wherein a concentration of the second material in the first region (108) is less than a concentration of the second material in the second region (106), and a thickness of the gate insulating layer in the first region (108) is less than the thickness of the gate insulating layer in the second region (106).
Yoon is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Kim. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yoon in the device of Kim because it will provide a device with good and improved electrical characteristics [0005] [0010].
Regarding claims 2-5, Kim in view of Yoon discloses a semiconductor device wherein a concentration of the first material (108) in the first region is greater than a concentration of the first material in the second region (106); wherein a concentration of the second material (106) in the gate insulating layer is greater in an area adjacent to the gate electrode layer (114) than in an area adjacent to the active area; wherein a concentration of the first material (108) in the gate insulating layer is smaller in an area adjacent to the gate electrode layer than in an area adjacent to the active area; wherein the first material [0034] contains at least one of silicon, carbon, nitrogen, or oxygen, and the second material contains oxygen [0030].
Yoon is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Kim. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yoon in the device of Kim because it will provide a device with good and improved electrical characteristics [0005] [0010].
Regarding claim 6, Kim in view of Yoon discloses a semiconductor device wherein each of the gate structures further comprises a capping layer (122)[0049] on a top surface of the gate electrode layer (114) and a sidewall of the second region.
Regarding claim 7, Kim in view of Yoon discloses a semiconductor device wherein a bottom surface of the capping layer (122) is not in contact with a top surface of the first region and a top surface of the second region (106).
Yoon is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Kim. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yoon in the device of Kim because it will provide a device with good and improved electrical characteristics [0005] [0010].
Regarding claim 8, Kim in view of Yoon discloses a semiconductor device further comprising nanosheets [0175] surrounded by each of the gate structures.
Regarding claim 9, Kim shows in FIG. 1-6H, a semiconductor device comprising: a substrate (110) comprising an element isolation layer (116) defining a cell region and a peripheral region [0018] around the cell region, and defining first active areas (117); and cell gate structures formed in a first trench (116) on the substrate (110) and intersecting the first active areas, in the cell region.
Kim differs from the claimed invention because he does not explicitly disclose a device wherein each of the cell gate structures comprises: a first barrier layer comprising a first region containing a first material and a second region containing a second material, wherein the first barrier layer is in the first trench and extends along a sidewall and a bottom surface of the first trench; a cell gate insulating layer containing the second material on a sidewall of the first barrier layer, and extending along the sidewall and the bottom surface of the first trench; a cell gate electrode layer on a sidewall of the cell gate insulating layer that fills the first trench; and a capping layer on a top surface of the cell gate electrode layer and a sidewall of the cell gate insulating layer, wherein a concentration of the second material in the first barrier layer is smaller than a concentration of the second material in the cell gate insulating layer.
Yoon discloses a device wherein each of the cell gate structures comprises: a first barrier layer (108) comprising a first region containing a first material and a second region (106) containing a second material, wherein the first barrier layer (108) is in the first trench and extends along a sidewall and a bottom surface of the first trench; a cell gate insulating layer containing the second material (106) on a sidewall of the first barrier layer, and extending along the sidewall and the bottom surface of the first trench; a cell gate electrode layer (114) on a sidewall of the cell gate insulating layer that fills the first trench; and a capping layer (122) on a top surface of the cell gate electrode layer and a sidewall of the cell gate insulating layer, wherein a concentration of the second material in the first barrier layer is smaller than a concentration of the second material in the cell gate insulating layer (106, 108 are formed of different material).
Yoon is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Kim. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yoon in the device of Kim because it will provide a device with good and improved electrical characteristics [0005] [0010].
Regarding claims 10-17, Kim in view of Yoon discloses a semiconductor device wherein with respect to a sidewall of the first trench , a thickness of the first barrier layer (108) is less than a thickness of the cell gate insulating layer; wherein a concentration of the second material (106) in the first barrier layer decreases as it gets closer to the first active area and increases as it gets closer to the cell gate electrode layer [0032]; wherein the cell gate insulating layer does not contain the first material; wherein the first material contains at least one of silicon, carbon, nitrogen, or oxygen, and the second material contains oxygen [0032]; further comprising a plurality of peripheral gate (114) structures formed on the substrate (100) and intersecting second active areas, in the peripheral region, wherein each of the peripheral gate structures comprises: a second barrier layer (110a) comprising a third region containing the first material and a fourth region containing the second material, on the second active area; a peripheral gate insulating layer containing the second material, on the second barrier layer, and a peripheral gate electrode layer (112a) disposed on the peripheral gate insulating layer; wherein a concentration of the second material in the second barrier layer (110a) [ Yoon, 0032] is less than a concentration of the second material in the peripheral gate insulating layer; wherein a thickness of the second barrier layer is less than a thickness of the peripheral gate insulating layer; further comprising: first and second source/drain regions [0157] in the first active areas; bit line structures on the substrate, and connected to the first source/drain region [0157]; and information storage units on the substrate, and connected to the second source/drain region [0157,0158].
Yoon is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Kim. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yoon in the device of Kim because it will provide a device with good and improved electrical characteristics [0005] [0010].
Regarding claim 18, Kim shows in FIG. 1-6H, for fabricating a semiconductor device, comprising: forming an element isolation layer (116) defining a plurality of active areas (117) on a substrate (110); forming a first trench intersecting at least a portion of the plurality of active areas in the substrate (110).
Kim differs from the claimed invention because he does not explicitly disclose a method of forming a barrier layer containing a first material along a sidewall and a bottom surface of the first trench; forming a gate insulating layer containing a second material different from the first material, on a sidewall of the barrier layer; and forming a gate electrode layer on a sidewall of the gate insulating layer and filling an inside of the first trench, wherein with respect to the sidewall of the first trench, a thickness of the barrier layer is less than or equal to half of a thickness of the gate insulating layer.
Yoon discloses a method of forming a barrier layer (108) containing a first material along a sidewall and a bottom surface of the first trench; forming a gate insulating layer containing a second material different (106) from the first material, on a sidewall of the barrier layer; and forming a gate electrode layer (114) on a sidewall of the gate insulating layer and filling an inside of the first trench, wherein with respect to the sidewall of the first trench, a thickness of the barrier layer is less than or equal to half of a thickness of the gate insulating layer.
Yoon is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Kim. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yoon in the device of Kim because it will provide a device with good and improved electrical characteristics [0005] [0010].
Regarding claims 19,20, Kim in view of Yoon discloses a method wherein a concentration of the first material (108) in the barrier layer is greater in an area adjacent to the active area than in the gate electrode layer, and a concentration of the second material (106) in the barrier layer is greater in an area adjacent to the gate electrode layer (112a) than in the active area; wherein the barrier layer contains at least one of silicon, silicon carbide, silicon nitride, silicon carbonitride, or silicon oxynitride, and the gate insulating layer contains silicon oxide [0032].
Yoon is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Kim. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Yoon in the device of Kim because it will provide a device with good and improved electrical characteristics [0005] [0010].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/ Primary Examiner, Art Unit 2813
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