DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
Claim(s) 1-4, 6, 9, 10, 12, 13 ,17, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liaw et al (US 20210098466).
Regarding Claim 1, Liaw teaches a memory structure (SRAM structure 30, Fig. 3, para [0031]), comprising: multiple memory cells (10_1 – 10_4, Fig. 3, para [0031]), each of the memory cells includes two active regions (103c & 103d, Fig. 3, para [0096]) extending lengthwise along a first direction (see figure 3 below) and four gate structures (143a-143d, Fig. 3, para [0034]) extending lengthwise along a second direction perpendicular to the first direction (see figure 3 below), each of the four gate structures extend across channel regions of the two active regions (see figure 3 below); and a pair of gate-cut dielectric features (109a – 109g, Fig. 3, para [0040]) extending lengthwise along the first direction at cell boundaries between each of the memory cells (see figure 3 below), each of the gate-cut dielectric features (109c & 109e & 109f, Fig. 3, para [0040]) contacts the each of the four gate structures in each of the memory cells (143 & 109b-109e, Fig. 5A para [0075]).
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Regarding Claim 2, Liaw teaches the memory structure of the memory structure (SRAM structure 30, Fig. 3, para [0031]) of wherein the each of the memory cells (10_1 – 10_4, Fig. 3, para [0032]) is defined by a cell height along the first direction (no direct element, Fig. 3, para [0032]) and a cell width along the second direction (no direct element, Fig. 3, para [0032]), and the cell height is greater than the cell width (no direct element, Fig. 3, para [0032]). (See figure below).
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The memory cells 10_1 through 10_4 can be redefined based on applicant’s claim language to form four vertically distinct memory cells.
Regarding Claim 4, Liaw teaches the memory structure of the memory structure (SRAM structure 30, Fig. 3, para [0031]) of wherein the each of the memory cells includes (10_1 – 10_4, Fig. 3, para [0032]): two pull-down transistors (PD-1) and two pass-gate transistors (PG-1) formed on a first active region of the two active regions, and two pull-up transistors (PU-1) formed on a second active region of the two active regions (See figure below).
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Regarding Claim 6, Liaw teaches the memory structure (SRAM structure 30, Fig. 3, para [0031]) of wherein in each of the memory cells (10_1 – 10_4, Fig. 3, para [0032]): two of the four gate structures (143a-143d, Fig. 3, para [0034]) include dielectric gates (151, Fig. 5A, para [0081]) extending across channel regions of a first active region of the two active regions (no specific element, see figures below) ,wherein the dielectric gates (151, Fig. 5A, para [0070]) cut through the first active regions along the second direction (no specific element, see figures below) and directly abut one of the gate-cut dielectric features (109, Fig. 5A, para [0064]), wherein the dielectric gates (151, Fig. 5A, para [0070]) are directly adjacent to pull-up transistors (PU-1) formed on the first active region along the first direction (no specific element, see figures below).
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Regarding Claim 9, Liaw teaches the memory structure of the memory structure (SRAM structure 30, Fig. 3, para [0031]) of wherein in each of the memory cells (10_1 – 10_4, Fig. 3, para [0032]), source/drain (S/D) features (135, Fig. 5B, para [0064]) formed over the two active regions (103a-103d, Fig. 5B, para [0064]) include epitaxial features (135, Fig. 5B, para [0065]) that directly contact the gate-cut dielectric features (109b-109e, Fig. 5B, para [0064]).
Regarding Claim 10, Liaw teaches The memory structure of claim 1 (SRAM structure 30, Fig. 3, para [0031]), wherein the gate-cut dielectric features and the gate structures have substantially coplanar top surfaces (planarization process discussed in para [0069] wherein the dummy gates 115 are planarized to the ILD layer 139; where later on the dummy gates are replaced by metal gates and pieces of the ILD are replaced by metal SD contacts).
Regarding Claim 12, Liaw teaches a memory structure (SRAM structure 30, Fig. 3, para [0031]), comprising: a first memory cell (10_2, Fig. 3, para [0032], explained in annotated figure in Claim 2) spanning between a first and a second gate-cut dielectric line (109c & 109e, Fig. 3, para [0064]), the first and the second gate-cut dielectric lines extend lengthwise along a first direction (151, Fig. 5A, para [0070]); and a second memory cell (10_3, Fig. 3, para [0032], explained in annotated figure in Claim 2) spanning between the second gate-cut dielectric line (109e, Fig. 3, para [0064]) and a third gate-cut dielectric line (109g, Fig. 3, para [0096]) the third gate-cut dielectric line extends lengthwise along the first direction (109g, Fig. 3, para [0096]), wherein the first memory cell (10_2, Fig. 3, para [0032], explained in annotated figure in Claim 2) includes: first and second active regions over a substrate (103c & 103d, Fig. 3, para [0041], including the area in between the active fins), the first and the second active regions extend lengthwise along the first direction (103c & 103d, Fig. 3, para [0041], including the area in between the active fins), and first gate structures over channel regions of the first and second active regions (143a-d, Fig. 3, para [0034]), the first gate structures extend lengthwise along a second direction perpendicular to the first direction (143a-d, Fig. 3, para [0034]), wherein the second memory cell (10_3, Fig. 3, para [0032], explained in annotated figure in Claim 2) includes: third and fourth active regions over the substrate (103e & 103g, Fig. 3, para [0096], including the area in between the active fins), the third and the fourth active regions extend lengthwise along the first direction (103e & 103g, Fig. 3, para [0096], including the area in between the active fins), and second gate structures over channel regions of the third and fourth active regions (143a-d, Fig. 3, para [0034]), the second gate structures extend lengthwise along the second direction (143a-d, Fig. 3, para [0034]), wherein the second gate-cut dielectric line directly contacts side surfaces of the first and second gate structures (109d, Fig. 5A, see figures below).
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Regarding Claim 13, Liaw teaches the memory structure of The memory structure (SRAM structure 30, Fig. 3, para [0031]) of wherein the first active region (103d, Fig. 3, para [0041]) and the first gate structures (143b, Fig. 3, para [0034]) form a first pass-gate transistor (PG-1, Fig. 3, para [0034]), a first pull-down transistor (PD-1, Fig. 3, para [0034]), a second pull-down transistor (PD-1, Fig. 3, para [0034]), and a second pass- gate transistor (PG-1, Fig. 3, para [0034]), wherein the second active region (103c, Fig. 3, para [0041]),and the first gate structures (143b, Fig. 3, para [0034]) form a first pull-up transistor (PU-1, Fig. 3, para [0035]) and a second pull-up transistor (PU-1, Fig. 3, para [0035]), wherein the third active region (103e, Fig. 3, para [0096]) and the second gate structures (no specific element, Fig. 3, see figure below) form a third pass- gate transistor (PG-1, Fig. 3, para [0034]) , a third pull-down transistor (PD-1, Fig. 3, para [0034]), a fourth pull-down transistor (PD-1, Fig. 3, para [0034]), and a fourth pass-gate transistor (PG-1, Fig. 3, para [0034]), wherein the fourth active region (103f, Fig. 3, para [0096]) and the second gate structures (no specific element, Fig. 3, see figure below) form a third pull- up transistor (PU-1, Fig. 3, para [0035]) and a fourth pull-up transistor (PU-1, Fig. 3, para [0035]) (see figure below).
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Regarding Claim 17, Liaw teaches A method of forming a memory device structure (100, Fig. 4A-4J, para [0044]), comprising: forming active regions over a substrate (103a-103d, Fig. 4A, para [0046]), the active regions extend lengthwise along a first direction(103a-103d, Fig. 4A, para [0046]); forming dummy gates over channel regions of the active regions (115a & 115b, Fig. 4F, para [0071]), the dummy gates extend lengthwise along a second direction perpendicular to the first direction (115a & 115b, Fig. 4F, para [0062]); forming source/drain (S/D) epitaxial features in S/D regions of the active regions (135, Fig. 4G, para [0065]) ; replacing first portions of the dummy gates with metal gates (143a-143d, Fig. 4I, para [0072]) and second portions of the dummy gates with dielectric gates (141, Fig 4I, para [0071]); forming gate-end dielectric lines cutting through the metal gates and the dielectric gates along the first direction (151, Fig. 4I, para [0070]); and forming S/D contacts over the S/D epitaxial features (161a-161h, Fig. 4J, para [0077]).
Regarding Claim 18, The method of claim 17 (100, Fig. 4A-4J, para [0044]), wherein the replacing of the first portions and the second portions of the dummy gates includes (115a & 115b, Fig. 4F, para [0062]): replacing the dummy gates with metal gates (143a-143d, Fig. 4I, para [0072]); and forming dielectric gates (141, Fig 4I, para [0071]) replacing portions of the metal gates, wherein the forming of the gate-end dielectric lines is performed after the forming of the dielectric gates (151, Fig. 4I, para [0075]).
For clarity of record; Liaw teaches that element 141 is below and surrounds the elements 143a-143d, we can assume therefore that the creation process of 141 is before the creation process of elements 143a-143d. Element 151 is described to have been created using a CMG (cut metal gate process) from which we can assume that places the creation of element 151 after the process for element 141 and the limitation is inherently met.
Claim Rejections - 35 USC § 103
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Liaw et al (US 20210098466) in view of Liaw (4) (US 20210202498).
Regarding Claim 3, Liaw teaches The memory structure of The memory structure (SRAM structure 30, Fig. 3, para [0031]).
Liaw does not explicitly teach wherein the cell height is a distance substantially equal to four times a distance between respective center lines of two adjacent gate structures along the first direction, wherein the cell width is a distance between respective center lines of two adjacent gate-cut dielectric features along the second direction.
However, Liaw (4) in an analogous field of similar endeavor teaches explicitly memory cell pitch measurement ratios (Liaw (4), para [0038]) that can be applied to Liaw in view of the applicant’s memory cell definitions. Liaw (4) also explains a rationale for differing memory cell pitches (Liaw (4), para [0022]).
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Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to modify Liaw in view of Liaw (4) to make simplify manufacturing process.
Claim(s) 5 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Liaw et al (US 20210098466) in view of Chen et al (US 20210098471).
Regarding Claim 5, Liaw teaches The memory structure of The memory structure (SRAM structure 30, Fig. 3, para [0031]) of wherein a first and a second memory cell of the multiple memory cells are adjacent to each other (see figure below), wherein the bit-line contact extends lengthwise over and across a gate-cut dielectric feature of the gate-cut dielectric features to land on source/drain (S/D) features of first pass-gate transistors in the first and second memory cells, wherein the bit-line bar contact extends lengthwise across the gate-cut dielectric feature to land on source/drain (S/D) features of second pass-gate transistors in the first and second memory cells (see figure below).
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Liaw does not explicitly teach wherein the first and second memory cell share a bit line or a bit-line bar contact.
However, in an analogous field, Chen teaches a gate contact (460A, Fig. 6, para [0037]) that is placed between pass-gate transistors of different memory cells (See figure below) where in it is implied that element 460A can include a bit line contact or complementary bit-line bar. This is due to Fig. 6 not including element 460I which is a bit line contact to PG-1 (Fig. 5, para [0037]). One of ordinary skill in the art would have a reasonable expectation of success (see figure below).
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Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to merge the S/D contacts of Liaw in view of Chen for the advantage of reducing parasitic current and simplifying aspects of the device building process.
It would have also been further obvious to one of ordinary skill in the art to wire the S/D contacts to contact a bit line and a complimentary bit line bar, for the purpose of allowing the circuit to work.
Regarding Claim 14, Liaw teaches The memory structure of claim 13, further comprising: source/drain (S/D) contacts (161, Fig. 5B, para [0036]) over S/D regions of the first (135, Fig. 5B, para [0079]), second (135, Fig. 5B, para [0079]), third (135, Fig. 5B, para [0079]), and fourth (135, Fig. 5B, para [0079]) active regions, the S/D contacts include: a bit line contact (161c, Fig. 5B, para [0036]) landing on a source region of the first pass-gate transistor (135, Fig. 5B, para [0036]) and a bit line bar contact (161f, Fig. 5B, para [0036]) landing on a source region of the second pass-gate transistor (135, Fig. 5B, para [0036]).
Liaw does not explicitly teach wherein the third pass-gate transistor includes a bit line contact landing on the same source region of the first pass-gate transistor, and the fourth pass-gate transistor has a bit line bar contact landing on a source region that includes the second pass-gate transistor and wherein the bit line contact (161c, Fig. 5B, para [0036]) and the bit line bar contact (161f, Fig. 5B, para [0036]) land on a top surface of the second gate-cut dielectric line.
However, in an analogous field, Chen teaches a gate contact that is placed between pass-gate transistors of different memory cells whose source regions can include a bit line contact and complementary bit-line bar. One of ordinary skill in the art would have a reasonable expectation of success.
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Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to merge the S/D contacts of Liaw in view of Chen for the advantage of reducing parasitic current and simplifying aspects of the device building process.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Liaw et al (US 20210098466) in view of Wen et al (US 11315933).
Regarding Claim 7, Liaw teaches the memory structure (SRAM structure 30, Fig. 3, para [0031]) of wherein in each of the memory cells (10_1 – 10_4, Fig. 3, para [0032]): the gate-cut dielectric features (109a – 109g, Fig. 3, para [0040]), the dielectric gates (151, Fig. 5A, para [0081]), and metal gates of the four gate structures (143a-143d, Fig. 3, para [0034]),
Liaw does not explicitly teach wherein the elements above are each formed over an isolation structure over a substrate, wherein the gate-cut dielectric features and the dielectric gates penetrate into the isolation structure, and the dielectric gates penetrate deeper into the isolation structure than the gate-cut dielectric features.
However, in a field of similar endeavor, Wen teaches an isolation structure over a substrate (Wen, 114, Fig. 7E, para (38)), wherein the gate-cut dielectric features (Wen, 174, Fig. 7E, para [89)) and the dielectric gates (Wen, 126, Fig. 7A, para (68)) penetrate into the isolation structure (Wen, 114, Fig. 7E, para (38)) and the dielectric gates penetrate deeper into the isolation structure than the gate-cut dielectric features (Wen, 126 & 174, Fig. 7E, para (94)).
Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application; to add an isolation structure over a substrate and vertically assemble the dielectric gate and gate-cut dielectrics wherein the dielectric gates extend further into the isolation layer than the gate-cut dielectrics to Liaw in view of Wen for the advantage of reduced current leakage and improved device performance.
Claim(s) 8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Liaw et al (US 20210098466) in view of Liaw (2) et al (US 20230013845).
Regarding Claim 8, Liaw teaches The memory structure of claim 1 (SRAM structure 30, Fig. 3, para [0031]), further comprising: bit line metals (no visual element, Fig. 3, para [0036]) electrically connected to source/drain (S/D) (135 & 161c & 161c, Fig. 3, para [0036]) features of pass-gate transistors in the multiple memory cells (161f & PG-2, Fig. 3, para [0036]), the pass-gate transistors are formed on an active region of the two active regions in each memory cell (PG-1, Fig. 3, para [0034]); and word line metals electrically connected to gates of the pass-gate transistors in the multiple memory cells (no associated visual element, Fig. 3, para [0026]).
Liaw does not explicitly teach wherein the bit line metals are global bit lines that continuously extend lengthwise along the first direction across a column of the multiple memory cells, the word line metals are global word lines that continuously extend lengthwise along the second direction across a row of the multiple memory cells, wherein the bit line metals are disposed in a first metal layer, the word line metals are disposed in a second metal layer, and the first metal layer is above the second metal layer.
However, in a field of similar endeavor, Liaw (2) teaches wherein the bit line metals are global bit lines (M3 & 1002 – 1022, Fig. 10, para [0124]-[0130]) that continuously extend lengthwise along the first direction across a column of the multiple memory cells (see figure below), the word line metals are global word lines (M2 & 911 & 919, Fig. 9, para [0117]-[0120] & [0135]) that continuously extend lengthwise along the second direction across a row of the multiple memory cells (see figure below), wherein the bit line metals are disposed in a first metal layer (M3, Fig. 13, para [0154]), the word line metals are disposed in a second metal layer (M2, Fig. 13, para [0155], and the first metal layer is above the second metal layer (M2 & M3, Fig. 13, para [0154]). As well as a rationale for bit line and word line layout (para [0023]).
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Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to add these metal layers in this order to include global bitlines and global wordlines to Liaw in view of Liaw (2) for the advantage reduced area footprint with reduced capacitance and resistivity (Liaw (2), para [0023]).
Regarding Claim 11, Liaw The memory structure of claim 1 (SRAM structure 30, Fig. 3, para [0031]), further comprising: a first metal layer having first metal lines extending lengthwise along the first direction, the first metal lines include local interconnects that electrically connect gates of different transistors in a memory cell together (161a-161h, Fig. 4J, para [0036]-[0038]), source/drain (S/D) features of different transistors in a memory cell together (161a-161h, Fig. 4J, para [0036]-[0038]), or gates and S/D features of different transistors in a memory cell together (161a-161h, Fig. 4J, para [0036]-[0038]).
Liaw does not explicitly teach wherein a second metal layer having second metal lines extending lengthwise along the second direction, the second metal lines include word line metals that electrically connect gates of different pass-gate transistors in different memory cells together; and a third metal layer having third metal lines extending lengthwise along the first direction, the third metal lines include bit line and bit line bar metals that electrically connect sources of different pass-gate transistors in different memory cells together.
However, in a field of similar endeavor Liaw (2) teaches wherein a second metal layer (902 – 926, Fig. 9, para [0111]) having second metal lines extending lengthwise along the second direction (see figure below), the second metal lines include word line metals that electrically connect gates of different pass-gate transistors in different memory cells together (911 & 919, Fig. 9, para [0111]); and a third metal layer (1002 – 1024, Fig. 10, para [0124]) having third metal lines extending lengthwise along the first direction (see figure below), the third metal lines include bit line (1010 & 1004, Fig. 10, para [0126] & [0128]) and bit line bar (1002 & 1012, Fig. 10, para [0125] & [0129]) metals that electrically connect sources of different pass-gate transistors in different memory cells together (see the figures below). As well as a rationale for bit line and word line layout (para [0023]).
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Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to add these metal layers in this order to include global bitlines and global wordlines to Liaw in view of Liaw (2) for the advantage of reduced area footprint with reduced capacitance and resistivity (Liaw (2), para [0023]).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Liaw et al (US 20210098466) in view of Liaw (3) et al (US 20240047522).
Regarding Claim 15, Liaw teaches The memory structure of The memory structure of wherein the first gate structures include first dielectric gate portions and first metal gate portions, wherein the first pull-up and the second pull-up transistors are sandwiched between the first dielectric gate portions (151, Fig. 3, para [0070]), wherein the second gate structures include second dielectric gate portions and second metal gate portions, wherein the third pull- up and the fourth pull-up transistors are sandwiched between the second dielectric gate portions (151, Fig. 3, para [0070]) (see figure below).
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Liaw does not teach wherein the first dielectric gate portions cut through the second active region to contact the first gate-cut dielectric line, or wherein the second dielectric gate portions cut through the fourth active region to contact the third gate-cut dielectric line.
However, in a field of similar endeavor, Liaw (3) teaches the use of a dummy gate that cuts through an active region (421a & 424a, Fig. 4B, para [0061]) in a logic cell, whose operation is analogous to a memory cell. Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to modify Liaw and extend the gate dielectric into cutting into the IS-1 active regions enough to contact the gate-cut dielectric for the well-known advantage of reducing leakage current and making memory operations more power efficient.
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Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Liaw et al (US 20210098466) in view of the following arguments.
Regarding Claim 20, Liaw teaches The method of claim 17 (100, Fig. 4A-4J, para [0044]), wherein the replacing of first portions and the second portions of the dummy gates includes (115a & 115b, Fig. 4F, para [0062]): replacing the dummy gates with metal gates (143a-143d, Fig. 4I, para [0072]), wherein the forming of the gate-end dielectric lines is performed before the forming of the dielectric gates (151, Fig. 4I, para [0075]).
Liaw does not explicitly teach wherein and forming dielectric gates replacing portions of the metal gates.
However, Liaw does disclose the knowledge of precise CMG (cut metal gate processes). Therefore, it would have been obvious to one of ordinary skill at the time of the effective filing date of the application, to set the metal gate electrode layer before the dielectric gates and use CMG processes to introduce the dielectric gate for the advantage of s a stable, patternable conductive layer for CMP and etch steps before the delicate high-k dielectric is applied.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.:
Design and Analysis of 6T, 8T, 10T SRAMS
The knowledge of different transistors schemes and different operational power demands is common to one of ordinary skill in the art.
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/ONASIS MORA/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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