DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received 7/1/26. Claims 1-20 are pending in this application. Claim 1 was amended in the amendment received 7/1/26.
Status of Claims
Claims 1-20 are pending in this application.
Response to Arguments
Applicant's arguments filed 7/1/26 have been fully considered but they are not persuasive.
Applicant argues (page 10) Lin does not disclose or render obvious at least these features of claim 1. In particular, The Office Action asserts that the gap 136 and the spacer 126 of Lin are the inner spacer and inner gate spacer as claimed, respectively (e.g., see FIG. 2H of Lin as annotated). However, the gap 136 is merely a void space formed between the inner spacer 126 and the source/drain epitaxial structure 139. In addition, claim 1 has been amended to recite that the inner spacer comprises an insulating material, as discussed during the Examiner Interview. Therefore, the Applicant respectfully submits that the gap 136 of Lin would not constitute an inner spacer as claimed. The Examiner respectfully disagrees. It is well known in the art that an air gap is an insulating material. See Rocklein (US 2019/0267383 [0034]) which teaches: “an insulating material such as silicon nitride, doped silicon nitride, a high-k dielectric material, or an air gap.” Clearly, an air gap is more than a void space. Hence, the reference teaches the limitations and arguments are not persuasive.
Specification
The objection to the specification has been withdrawn in light of the amendment received 7/1/26.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-4 and 7 are rejected under pre-AIA 35 U.S.C. 103 as being unpatentable over Lin et al. (US Patent Application Publication No 2023/0123484) hereinafter referred to as Lin.
Per Claim 1 Lin discloses a semiconductor device (see figure 4B), comprising
a substrate (102) including an active pattern (130/134);
a channel pattern (106) on the active pattern, the channel pattern comprising a plurality of semiconductor patterns (top middle and bottom) that are spaced apart from each other; (see figure 4B) The examiner notes that the term "on" includes "directly on" (no intermediate materials, elements or space disposed therebetween) and "indirectly on" (intermediate materials, elements or space disposed therebetween)
a source/drain pattern (139) electrically connected to the plurality of semiconductor patterns; The examiner notes that the term "electrically connected" includes both ohmic (metallic) connection as well as capacitive (insulating) connection. The examiner notes that the term "connected" includes "directly connected" (no intermediate materials, elements or space disposed therebetween) and "indirectly connected " (intermediate materials, elements or space disposed therebetween)
an inner gate electrode (gate electrode layer (not shown), surrounds (144)) between adjacent first (middle) and second (bottom) semiconductor patterns of the plurality of semiconductor patterns; (see figure 2H)
an inner gate insulating layer (141/126) between the inner gate electrode and the first and second semiconductor patterns;
an inner high-k dielectric layer (142) between the inner gate electrode and the inner gate insulating layer; and
an inner spacer (air gap (136), see [0062]) between the inner gate insulating layer (141/126) and the source/drain pattern (139), wherein the inner spacer comprises an insulating material (The Examiner notes that it is well known in the art that air gaps are insulating Rocklein (US 2019/0267383 [0034]) is provided as a teaching reference).
wherein the inner gate insulating layer (141/126) comprises:
an upper insulating layer (141 upper) between the inner gate electrode and the second semiconductor pattern;
a lower insulating layer (141 upper) between the inner gate electrode and the first semiconductor pattern; and
an inner gate spacer (126) between the inner gate electrode and the source/drain pattern,
wherein a first thickness of the inner gate spacer (126) at a center portion of the inner gate spacer is greater than a second thickness of the upper insulating layer (141 upper) or the lower insulating layer (141 lower), and (see figure 6B)
and a third thickness of the inner spacer (136).
Lin does not teach where the third thickness of the inner spacer is greater than the first thickness of the inner gate spacer
Notwithstanding, one of ordinary skill in the art would have been led to the recited relative dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(IV)(B).
Per Claim 2 Lin discloses the device of claim 1 (see figure 4B) including the first thickness
Lin does not teach where the first thickness ranges from 1.0Å to 15.0Å
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(IV)(B).
Per Claim 3 Lin discloses the device of claim 1 (see figure 4B) including the second thickness
Lin does not teach where the second thickness ranges from 1.0Å to 10.0Å
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(IV)(B).
Per Claim 4 Lin discloses the device of claim 1 (see figure 4B) including the third thickness.
Lin does not teach where the third thickness ranges from 10.0Å to 25.0Å.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(IV)(B).
Per Claim 7 Lin discloses the device of claim 1 (see figure 4B) including where the inner spacer (136) comprises: a first sidewall in contact with the source/drain pattern (139); and a second sidewall in contact with the inner gate spacer (126), wherein each of the first and second sidewalls has a curved surface (as shown in figure 2H).
Allowable Subject Matter
Claim 5-6 and 8-13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 14-20 allowed.
The following is an examiner's reasons for the indication of allowable subject matter. No prior art was found that neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination.
The closest prior art appears to be Lin (cited above) which teaches an analogous device ( as above, see claim 1) but does not teach a second source/drain pattern electrically connected to the second channel pattern; a first inner gate electrode between adjacent semiconductor patterns of the plurality of semiconductor patterns of the first channel pattern; a second inner gate electrode between adjacent semiconductor patterns of the plurality of semiconductor patterns of the second channel pattern; a first inner gate insulating layer between the first inner gate electrode and the adjacent semiconductor patterns of the first channel pattern; a second inner gate insulating layer between the second inner gate electrode and the adjacent semiconductor patterns of the second channel pattern; a first inner high-k dielectric layer between the first inner gate electrode and the first inner gate insulating layer; and a second inner high-k dielectric layer between the second inner gate electrode and the second inner gate insulating layer, wherein the first inner gate insulating layer comprises: a first upper insulating layer on a top surface of the first inner gate electrode; a first lower insulating layer on a bottom surface of the first inner gate electrode; and a first inner gate spacer on both sidewalls of the first inner gate electrode, wherein the second inner gate insulating layer comprises: a second upper insulating layer on a top surface of the second inner gate electrode; a second lower insulating layer on a bottom surface of the second inner gate electrode; and a second inner gate spacer on both sidewalls of the second inner gate electrode, wherein the semiconductor device further comprises: an inner spacer between the first inner gate spacer and the first source/drain pattern, wherein a thickness of the second inner gate spacer is less than a sum of a thickness of the first inner gate spacer and a thickness of the inner spacer as recited by independent claim 14, in combination with the other elements/steps of the claim.
The closest prior art appears to be Lin (cited above) which teaches an analogous device (as above, see claim 1) but does not teach an outer gate insulating layer on the uppermost semiconductor pattern; a high-k dielectric layer between the gate electrode and the gate insulating layer; and an inner spacer between the inner gate insulating layer and the source/drain pattern, wherein the inner gate insulating layer comprises: an upper insulating layer on a top surface of the inner gate electrode; a lower insulating layer on a bottom surface of the inner gate electrode; and an inner gate spacer between the inner gate electrode and the inner spacer, wherein each of the upper insulating layer and the lower insulating layer comprises: body portions parallel to a top surface or bottom surface of the inner gate electrode; and tail portions on sides of the body portions, wherein the body portion has a first length in a vertical direction that is perpendicular to the substrate, wherein the tail portion has a second length in the vertical direction, and wherein a variation of the second length over a predetermined horizontal distance is greater than a variation of the first length over the predetermined horizontal distance as recited by independent claim 18, in combination with the other elements/steps of the claim.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
Rocklein (US 2019/0267383) is provided as a teaching reference, where it teaches that and air gap is an insulating material, see [0034].
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMI VALENTINE MILLER whose telephone number is (571)272-9786. The examiner can normally be reached Monday-Thursday 7am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jami Valentine Miller/ Primary Examiner, Art Unit 2818
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