DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending in this application.
Information Disclosure Statement
Acknowledgment is made that the information disclosure statement has been received and considered by the examiner. If the applicant is aware of any prior art or any other co-pending applications not already of record, he/she is reminded of his/her duty under 37 CFR 1.56 to disclose the same.
Drawings
There are no objections or rejections to the drawings.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 15 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Ku et al. (US Patent Application Publication No 2023/0178589) hereinafter referred to as Ku.
Per Claim 1 Ku discloses a semiconductor device, comprising
a stacked structure of a first device level (102) and a second device level (120);
a middle back end of a line (BEOL) level (110, lower, see figure 8) positioned between the first device level and the second device level (as shown in figures 1 and 8), the middle back end of the line (BEOL) level includes
a first wiring layer (110a) in electrical communication with the first device level and (The examiner notes that the term " electrical communication" includes both ohmic (metallic) communication as well as capacitive (insulating) communication.)
a second wiring layer (110c) in electrical communication with the second device level,
wherein a second pitch for metal lines (116, part of 110c, see figures 1 and 8) in the second wiring layer is greater than a first pitch for metal lines (116, part of 110a, see figures 1 and 8) in the first wiring layer (see [0028]); and
a frontside back end of the line (BEOL) level (110 upper, see figure 8) above the second device level
Per Claim 15 Ku discloses a method of forming a semiconductor device, comprising
forming first wiring layers (110a) on a first device level;
forming second wiring layers (110c) on the first wiring layers to provide a middle back end of a line (BEOL) level (110),
wherein a second pitch for metal lines (116, part of 110c, see figures 1 and 8) in the second wiring layers is greater than a first pitch for metal lines (116, part of 110a, see figures 1 and 8) in the first wiring layers; and
forming a second device level (120) on the middle back end of the line (BEOL) level. (see figures 1 and 8)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 9, 13-14 and 16 is rejected under pre-AIA 35 U.S.C. 103 as being unpatentable over Ku as applied to claim 1 above in view of Haran et al. (US Patent Application Publication No 2023/0420360) hereinafter referred to Haran.
Per Claim 9 Ku discloses a semiconductor device, comprising
a stacked structure of a first device level (102) and a second device level (120);
a middle back end of a line (BEOL) level (110, lower, see figure 8) positioned between the first device level and the second device level (as shown in figures 1 and 8), the middle back end of the line (BEOL) level includes
a first wiring layer (110a) in electrical communication with the first device level and
a second wiring layer (110c) in electrical communication with the second device level,
wherein a second pitch for metal lines (116, part of 110c, see figures 1 and 8) in the second wiring layer is greater than a first pitch for metal lines (116, part of 110a, see figures 1 and 8) in the first wiring layer; and
a frontside back end of the line (BEOL) level (110 upper, see figure 8) in electrical communication with the second device level
Ku does not teach where a backside power network is in electrical communication with the first device level.
Haran teaches an analogous device including a backside power network is in electrical communication with a first device level (see figure 1 and [0041]).
All of the component parts are known in Ku and Haran. The only difference is the combination of the old elements into a single device, by using the backside power network of Haran in the device of Ku. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the backside power network of Haran in the device of Ku, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Per Claim 13 Ku in view of Haran discloses the device of claim 9 including where vertically orientated electrical wiring is in the first wiring layer (110a). (as described in [0022])
Per Claim 14 Ku in view of Haran discloses the device of claim 13 including where laterally orientated electrical wiring (horizontal interconnect structures) is in the second wiring layer. (as described in [0022])
Per Claim 16 Ku discloses the device of claim 15 including he first device level
Ku does not teach forming a backside power network on the first device level.
Haran teaches an analogous device including forming a backside power network on the first device level (see figure 1 and [0041]).
All of the component parts are known in Ku and Haran. The only difference is the combination of the old elements into a single device, by using the backside power network of Haran in the device of Ku. It would have been obvious to one having ordinary skill in the art at the time the invention was made to use the backside power network of Haran in the device of Ku, since a person with ordinary skill has good reason to pursue the known options within his or her technical grasp. KSR International Co. v. Teleflex Inc., 550 U.S.--, 82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claims 2-8 10-12, 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
Hsaio (2025/0046756 and 2025/0357429) are cited as analogous art teaching all features except the frontside back end of the line (BEOL) level (110 upper, see figure 8) above the second device level.
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMI VALENTINE MILLER whose telephone number is (571)272-9786. The examiner can normally be reached on Monday-Thursday 7am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached on (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jami Valentine Miller/Primary Examiner, Art Unit 2818
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