DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed 16 June 2026 is acknowledged. Claims 18-20 have been canceled. Claim 12 has been amended. Claims 21-23 have been added. Claims 1-17 and 21-23 are pending.
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-17, in the reply filed on 16 June 2026 is acknowledged.
Claims 18-20 would have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim; however, claims 1-18 were canceled in the election made without traverse in the reply filed on 16 June 2026.
Information Disclosure Statement
Information disclosure statement filed 18 August 2025 has been fully considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: PACKAGE SUBSTRATE[[,]] AND SEMICONDUCTOR DEVICE COMPRISING A PACKAGE SUBSTRATE.
Claim Objections
Claims 4 and 14 are objected to because of the following informalities:
Claims 4 and 14 recite the limitation, “a second semiconductor die of the semiconductor dies a capacitor die.” This appears to contain a typographical error and may be corrected as, “a second semiconductor die of the semiconductor dies comprises a capacitor die.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation, “the core substrate.” There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 6, 7, 10, 12, 17, and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US Patent Application Publication 2022/0384320, hereinafter Lee ‘320).
With respect to claim 1, Lee ‘320 teaches (FIG. 11) a package substrate as claimed, comprising:
a first dielectric layer (171 and 172) comprising first electrical interconnect (174 and 176) ([0039]);
a second dielectric layer (110, 121, and 123) comprising second electrical interconnect (111, 113, and 128) ([0025-0026]); and
a core layer, situated between the first dielectric layer (171 and 172) and the second dielectric layer (110, 121, and 123), the core layer comprising a plurality of semiconductor dies (151 and 155) stacked one above another between the first dielectric layer and the second dielectric layer, wherein a first semiconductor die (151) of the semiconductor dies is a capacitor die electrically connected to the first electrical interconnect (174 and 176) of the first dielectric layer ([0049]).
With respect to claim 2, Lee ‘320 teaches wherein a second semiconductor die (155) of the semiconductor dies (151 and 155) is a capacitor die electrically connected to the second electrical interconnect (111, 113, and 128) of the second dielectric layer (110, 121, and 123) ([0049]).
With respect to claim 6, Lee ‘320 teaches wherein the semiconductor dies (151 and 155) are located within a cavity of the core substrate; the first dielectric layer (171 and 172) and the second dielectric layer (110, 121, and 123) are formed on opposite sides of the cavity respectively ([0049]).
With respect to claim 7, Lee ‘320 teaches wherein the core layer further comprises: an adhesive layer (153), formed between two adjacent semiconductor dies (151 and 155) to bond the two adjacent semiconductor dies ([0049]).
With respect to claim 10, Lee ‘320 teaches wherein the core layer further comprises: a conductive structure (160), penetrating through the core layer and electrically connected between the first dielectric layer (171 and 172) and the second dielectric layer (110, 121, and 123) ([0023]).
With respect to claim 12, Lee ‘320 teaches (FIG. 11) a semiconductor device as claimed, comprising:
a package substrate (1000) having a core layer, the core layer comprising an embedded capacitor device (150 and 156-159) ([0023, 0030, 0052-0053, 0091]), the embedded capacitor device comprising:
a plurality of semiconductor dies (151 and 155) stacked one above another, a first semiconductor die (151) of the semiconductor dies is a capacitor die with exposed terminal electrodes (159) ([0049, 0053]); and
a plurality of adhesive layers (153) alternately stacked with the semiconductor dies (151 and 155), wherein each adhesive layer is bonded to two semiconductor dies on opposite sides of the adhesive layer respectively ([0049]); and
a semiconductor chip (310), arranged at a first side of the package substrate (1000) and electrically connected to the embedded capacitor device (150 and 156-159) ([0093]).
With respect to claim 17, Lee ‘320 teaches further comprising: a circuit board (100), arranged at a second side of the package substrate (1000) opposite to the first side, wherein the core layer is located between the first side and the second side ([0025]).
With respect to claim 21, Lee ‘320 teaches wherein the plurality of semiconductor dies (151 and 155) are laterally surrounded by and in contact with a filling material (180) ([0023]).
With respect to claim 22, Lee ‘320 teaches wherein a height of a stack (150 and 156-159) of the plurality of semiconductor dies (151 and 155) is substantially equal to a thickness of the core layer ([0023, 0030, 0052-0053]).
With respect to claim 23, Lee ‘320 teaches wherein the package substrate (1000) comprises: a first dielectric layer (171 and 172) comprising a first electrical interconnect (174 and 176), the first dielectric layer is disposed on a side of the core layer; and a second dielectric layer (110, 121, and 123) comprising second electrical interconnect (111, 113, and 128), the second dielectric layer is disposed on an opposite side of the core layer, and wherein a stack (150 and 156-159) of the plurality of semiconductor dies (151 and 155) is arranged to provide a conductive path between the first dielectric layer and the second dielectric layer ([0025-0026, 0039, 0049]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘320 as applied to claims 1 and 12 above, and further in view of Yu et al. (US Patent Application Publication 2018/0269188, hereinafter Yu ‘188).
With respect to claims 3 and 13, Lee ‘320 teaches the device as described in claims 1 and 12 above with the exception of the additional limitations wherein a second semiconductor die of the semiconductor dies is a dummy die electrically isolated from the first electrical interconnect of the first dielectric layer and the second electrical interconnect of the second dielectric layer; and wherein a second semiconductor die of the semiconductor dies is a dummy die.
However, Yu ‘188 teaches (FIG. 19) a second semiconductor die (802) of semiconductor dies (118 and 802) is a dummy die electrically isolated from electrical interconnects (126) of a dielectric layer (128) to provide good thermal conductivity ([0085]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a second semiconductor die of the semiconductor dies of Lee ‘320 as a dummy die electrically isolated from the first electrical interconnect of the first dielectric layer and the second electrical interconnect of the second dielectric layer; and as a dummy die as taught by Yu ‘188 to provide good thermal conductivity.
Claims 4, 8, 9, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘320 as applied to claims 1, 7, and 12 above, and further in view of Kim et al. (US Patent Application Publication 2010/0148316, hereinafter Kim ‘316).
With respect to claims 4 and 14, Lee ‘320 teaches the device as described in claims 1 and 12 above with the exception of the additional limitations wherein the first semiconductor die comprises a through-substrate via structure, and a second semiconductor die of the semiconductor dies a capacitor die electrically connected to the first electrical interconnect of the first dielectric layer through the through-substrate via structure; and wherein the first semiconductor die comprises a through-substrate via structure, and a second semiconductor die of the semiconductor dies a capacitor die electrically connected to the through-substrate via structure.
However, Kim ‘316 teaches (FIG. 8) a first semiconductor die (300) comprising a through-substrate via structure (314), and a second semiconductor die (302) comprising a capacitor die (when selected from among “capacitors”; [0077]) electrically connected to a first electrical interconnect (320 and 322) of a first dielectric layer (324) through the through-substrate via structure to form functional electrical circuits according to an electrical design and function of the semiconductor dies ([0077-0078, 0080]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the first semiconductor die of Lee ‘320 comprising a through-substrate via structure, and a second semiconductor die of the semiconductor dies a capacitor die electrically connected to the first electrical interconnect of the first dielectric layer through the through-substrate via structure; and comprising a through-substrate via structure, and a second semiconductor die of the semiconductor dies a capacitor die electrically connected to the through-substrate via structure as taught by Kim ‘316 to form functional electrical circuits according to an electrical design and function of the semiconductor dies.
With respect to claims 8, 9, and 15, Lee ‘320 teaches the device as described in claims 7 and 12 above with the exception of the additional limitations wherein the adhesive layer comprises polymer adhesive; wherein the adhesive layer is photosensitive; and wherein the adhesive layer comprises polymer adhesive or photosensitive adhesive.
However, Kim ‘316 teaches polymer adhesive or photosensitive adhesive as art-recognized materials suitable for the intended use as adhesive layers (102 and 116) ([0040, 0044]). Further, the selection of a known material based on its suitability for its intended use supports a prima facie obviousness determination. Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) and In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960). See MPEP 2144.07.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the adhesive layer of Lee ‘320 comprising polymer adhesive, as photosensitive, and comprising polymer adhesive or photosensitive adhesive as taught by Kim ‘316 as art-recognized materials suitable for the intended use as adhesive layers.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘320 as applied to claim 1 above, and further in view of Fang et al. (US Patent Application Publication 2025/0038145, hereinafter Fang ‘145).
With respect to claim 5, Lee ‘320 teaches the device as described in claim 1 above with the exception of the additional limitation wherein a thickness of the core layer is greater than or equal to 800 micrometers.
However, Fang ‘145 teaches (FIG. 3) a thickness of a core layer (102) greater than or equal to 800 micrometers to reduce warpage of the package ([0027-0028]). Further, such a modification would have involved a mere change in size or proportion of a component. A change in size or proportion is generally recognized as being with the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP 2144.04 IV. A.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed a thickness of the core layer of Lee ‘320 greater than or equal to 800 micrometers as taught by Fang ‘145 to reduce warpage of the package.
Further, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon a particular chosen distance or upon another variable recited in the claim, Applicant must show that the chosen variable is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘320 as applied to claim 1 above, and further in view of Pandit et al. (US Patent Application Publication 2022/0375898, hereinafter Pandit ‘898).
With respect to claim 11, Lee ‘320 teaches the device as described in claim 1 above with the exception of the additional limitation wherein at least one of the semiconductor dies has a plurality of three-dimensional capacitors formed by a dynamic random-access memory (DRAM) process.
However, Pandit ‘898 teaches semiconductor dies (102) having a plurality of three-dimensional capacitors (108) formed by a DRAM process to obtain appropriate capacitor coupling that enables a programmable (e.g., tunable) solution for meeting capacitance value and/or frequency response specifications ([0049, 0106]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed at least one of the semiconductor dies of Lee ‘320 having a plurality of three-dimensional capacitors formed by a dynamic random-access memory (DRAM) process as taught by Pandit ‘898 to obtain appropriate capacitor coupling that enables a programmable (e.g., tunable) solution for meeting capacitance value and/or frequency response specifications.
The expression, “formed by a dynamic random-access memory (DRAM) process,” is taken to be a product-by-process limitation and is given limited patentable weight. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lee ‘320 as applied to claim 12 above, and further in view of Gardner et al. (US Patent Application Publication 2022/0181315, hereinafter Gardner ‘315).
With respect to claim 16, Lee ‘320 teaches the device as described in claim 12 above with the exception of the additional limitation wherein the semiconductor chip comprises a gate-all-around (GAA) transistor structure.
However, Gardner ‘315 teaches (FIG. 4a) stacking semiconductor chips (104) comprising gate-all-around transistor structures ([0033]) as a manner to increase memory density ([0006]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor chip of Lee ‘320 comprising a gate-all-around (GAA) transistor structure as taught by Gardner ‘315 as a manner to increase memory density.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern.
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/C.M.R./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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