Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 7/6/26 is acknowledged.
Claims 3-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/6/26.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 10-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US PGPub 2022/0406817)
Claim 1: Park teaches a display device (Fig. 6, 8A), comprising: a substrate (SUB) including a display area (DPA) including a plurality of sub pixels (SPXn) [0089] is disposed and a non-active area (NDA/PDA) adjacent to the active area; a plurality of pad electrodes (PAD) disposed on the substrate in the non-active area to transmit a signal to the plurality of sub pixels and each including a first conductive layer (PAD_L), a second conductive layer (PAD_U) disposed on the first conductive layer, and a third conductive layer (PDC) disposed on the second conductive layer; a first passivation layer (PV1) extending from the active area and disposed on a portion of the first conductive layer; and a second passivation layer (PAS1) extending from the active area and covering an end of the second conductive layer.
Claim 2: Park teaches (Fig. 8A) the first passivation layer disposed on the first conductive layer of each of the plurality of pad electrodes has a contact hole, and the second conductive layer and the first conductive layer are in contact with each other by a contact surface thereof in the contact hole.
Claim 10: Park teaches (Fig. 8A) the first passivation layer encloses the first conductive layer.
Claim 11: Park teaches (Fig. 8A) the second passivation layer surrounds the second conductive layer.
Claim 12: Park teaches (Fig. 8A) a plurality of metal layers disposed between the plurality of pad electrodes and the substrate, wherein the plurality of metal layers include a first metal layer (ML1/PW1) and a second metal layer (ML2/PW2) disposed on the first metal layer.
Claim 13: Park teaches [0089-0091] a plurality of transistors disposed at each of the plurality of sub pixels; and a plurality of capacitors disposed in the plurality of sub pixels [0119], wherein the first metal layer is formed of a same material as gate electrodes of the plurality of transistors and the second metal layer is formed of a same material as capacitor electrodes of the plurality of capacitors.
Claim 14: Park teaches (Fig. 6, 8A)an area of the plurality of metal layers on a plane is smaller than an area of the plurality of pad electrodes on the plane.
Claim 15: Park teaches (Fig. 6, 8A)the plurality of metal layers is electrically floated.
Claim 16: Park teaches (Fig. 8A) [0180, 0184] a plurality of transistors disposed in each of the plurality of sub pixels, wherein the first conductive layer is formed of a same material as source electrodes and drain electrodes of the plurality of transistors.
Claim 17: Park teaches (Fig. 8A) the first passivation layer is disposed on the plurality of transistors.
Claim 18: Park teaches [0133, 0140] a plurality of light emitting diode disposed in each of the plurality of sub pixels; and a reflection plate disposed below the light emitting diode, wherein the second conductive layer is formed of a same material as the reflection plate [0181].
Claim 19: Park teaches (Fig. 6) comprising a connection electrode (CNE1) electrically connecting the reflection plate and the plurality of light emitting diodes, wherein the third conductive layer is formed of a same material as the connection electrode [0182].
Claim 20: Park teaches (Fig. 6) the second passivation layer is disposed on the reflection plate.
Claim 21: Park teaches [0089] the active area further includes a plurality of gate driving areas extending from the plurality of sub pixels and including a gate driver.
Claim 22: Park teaches [0116] active layers of a plurality of transistors disposed at the plurality of sub pixels and active layers of a plurality of transistors disposed at the gate driver include at least one of oxide semiconductor, amorphous silicon, low temperature polysilicon, and polysilicon.
Claim 23: Park teaches (Fig. 5, 6, 8A) the plurality of transistors disposed in the gate driver includes the active layers different from the active layers of the subpixel.
Claim 24: Park teaches (Fig. 8A) the plurality of metal layers is insulated from the plurality of pad electrodes.
Claim 25: Park teaches a display device (Fig. 6, 8A) (see claim 1), a substrate defined by a display area including a plurality of sub pixels and a non-active area adjacent to the active area; a first pad electrode comprising first, second and third conductive layers and disposed in the non-active area to transmit a signal to the plurality of sub pixels and; and a first passivation layer extending from the active area, disposed on the first conductive layer and having at least one contact hole, wherein the first conductive layer and the second conductive layer are in contact through the at least one contact hole.
Claim 26: Park teaches (Fig. 8A) a second passivation layer extending from the active area and covering one end of the second conductive layer.
Claim 27: Park teaches (Fig. 8A) a first planarization layer disposed on the first conductive layer and the first passivation layer.
Claim 28: Park teaches(Fig. 8A) the first planarization layer covers a portion of the first passivation layer where the first passivation layer overlaps the first pad electrode.
Claim 29: Park teaches (Fig. 8A) the second passivation layer is disposed on the second conductive layer and the first planarization layer.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at 5712721705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SARAH K SALERNO/Primary Examiner, Art Unit 2814
Prosecution Insights