Prosecution Insights
Last updated: July 17, 2026
Application No. 18/583,336

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §102§103§112
Filed
Feb 21, 2024
Priority
Jul 13, 2023 — JP 2023-115138
Examiner
CHAN, CANDICE
Art Unit
2813
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kabushiki Kaisha Toshiba
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
400 granted / 551 resolved
+4.6% vs TC avg
Strong +19% interview lift
Without
With
+19.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
35 currently pending
Career history
613
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
79.0%
+39.0% vs TC avg
§102
11.2%
-28.8% vs TC avg
§112
6.0%
-34.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 551 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This Office action is in response to the election filed 9 June 2026. Claims 1-13 are currently pending; claims 10-13 have been withdrawn by Applicant. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I, claims 1-9, in the reply filed on 9 June 2026 is acknowledged. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites the limitation "the third semiconductor part side" in lines 3-4. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the above limitation is assumed to refer to a side of the third semiconductor part. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 3-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2022/015533 A1 to Gangi et al. (hereinafter “Gangi”). Regarding independent claim 1, Gangi (Fig. 1) discloses a semiconductor device, comprising: a semiconductor layer 11/12/13 (¶ 0029) including a first semiconductor part 11 (¶ 0029) of a first conductivity type (¶ 0029 - n-type), a second semiconductor part 12 (¶ 0029) located on the first semiconductor part 11, the second semiconductor part being of a second conductivity type (¶ 0029 - p-type), a third semiconductor part 13 (¶ 0029) located on the second semiconductor part 12, the third semiconductor part being of the first conductivity type (¶ 0029 - n-type), and a mesa part (including 11a, portions of 12/13 above 11a) including the third semiconductor part 13, the second semiconductor part 12, and a portion of the first semiconductor part 11a (¶ 0030), the mesa part extending in a first direction (Z-direction); a gate electrode 61 (¶ 0032) facing a side surface (right side) of the mesa part; and a first insulating part 41b (¶ 0032) located between the gate electrode 61 and the side surface (right side) of the mesa part, the gate electrode 61 including a first side surface portion (portion of left side facing 12) facing a region of the side surface (right side) of the mesa part including at least the second semiconductor part 12 (Fig. 1), a second side surface portion (right side of 61) positioned at a side opposite to the first side surface portion in a second direction (X-direction) orthogonal to the first direction, a bottom portion (bottom surface of 61) oblique to the first and second side surface portions, the bottom portion connecting the first side surface portion (left side of 61) and the second side surface portion (right side of 61), a first corner portion (left bottom corner of 61) positioned between the first side surface portion (left side of 61) and the bottom portion (bottom surface of 61), and a second corner portion (right bottom corner of 61) positioned between the second side surface portion (right side of 61) and the bottom portion, an angle Ɵ (annotated Fig. 1 below) between a first straight line A (annotated Fig. 1 below) and a second straight line B (annotated Fig. 1 below) being not more than 60°, the first straight line A being a straight line extending in the first direction (Z-direction) and passing through the first corner portion (Fig. 1), the second straight line B being a straight line passing through the first and second corner portions (Fig. 1). PNG media_image1.png 640 834 media_image1.png Greyscale Regarding claim 3, Gangi (Fig. 1) discloses the device according to claim 1, further comprising: a conductive member 62 (¶ 0052) facing the second side surface portion (right side of 61) of the gate electrode 61 in the second direction (X-direction) and extending further downward in the first direction (Y-direction) than the bottom portion of the gate electrode 61 (Fig. 1); and a second insulating part (portion of 41 between 62 and right side of 61) positioned between the conductive member 62 and the second side surface portion (right side of 61). Regarding claim 4, Gangi (Fig. 1) discloses the device according to claim 3, further comprising: a first electrode 52 (¶ 0052) located on the mesa part (including 11a, portions of 12/13 above 11a), the first electrode 52 being electrically connected with the third semiconductor part 13 (Fig. 1), the conductive member 62 being electrically connected with the first electrode 52 (¶ 0052). Regarding claim 5, as best understood, Gangi (Fig. 1) discloses the device according to claim 1, wherein a position in the first direction (Z-direction) of an upper end of the first side surface portion (upper end of portion of left side of 61 facing 12) is positioned further toward the third semiconductor part side (right side of 13 of mesa part) than a boundary between the second semiconductor part 12 and the third semiconductor part 13 (boundary between 12/13 located in left portion of mesa part to the left of portion 52a; Fig. 1). Regarding claim 6, Gangi (Fig. 1) discloses the device according to claim 1, wherein a length in the first direction (Z-direction) of the second side surface portion (right side of 61) is greater than a length in the first direction (Z-direction) of the first side surface portion (left side of 61; Fig. 1). Regarding claim 7, Gangi (Fig. 1) discloses the device according to claim 1, wherein an angle between the first side surface portion (left side of 61) and the bottom portion (bottom of 61) inside the gate electrode 61 is greater than 90° (as measured in lower left corner of 61; Fig. 1). Regarding claim 8, Gangi (Fig. 1) discloses the device according to claim 1, wherein an angle between the second side surface portion (right side of 61) and the bottom portion (bottom of 61) inside the gate electrode 61 is less than 90° (as measured in lower right corner of 61; Fig. 1). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Gangi. Regarding claim 2, Gangi (Fig. 1) discloses the device according to claim 1, however, does not expressly disclose: wherein the angle between the first straight line and the second straight line is not more than 40°. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the above angle range of not more than 40° in the device of Gangi since variances in manufacturing steps (e.g., see Figs. 11A-11B - the removal step of portions of 41, prior to deposition of gate electrode material) affect the recited angle and dimensions of the subsequently deposited gate electrode and could result in the above claimed range. Additionally, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Here, the above defined angle is considered a mere dimensional limitation. The instant disclosure is silent as to a particular unobvious purpose, unexpected result, or criticality of the above dimensional limitation and thus is found to be prima facie obvious. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Gangi as applied to claim 1 above, and further in view of US 2009/0263952 A1 to Viswanathan et al. (hereinafter “Viswanathan”). Regarding claim 9, Gangi (Fig. 1) discloses the device according to claim 1, however fails to expressly disclose wherein a maximum thickness in the second direction (X-direction) of the first insulating part between the first side surface portion (left side of 61) of the gate electrode and the side surface (left side) of the mesa part is less than a maximum thickness in the second direction (X-direction) of the first insulating part between the bottom portion of the gate electrode 61 and the side surface (right side) of the mesa part (Fig. 1 - Gangi discloses the above recited maximum thicknesses are approximately the same). In the same field of endeavor, Viswanathan (Fig. 4G) discloses a device including a gate electrode 24 (¶ 0027) and first insulating part 54 (¶ 0034), wherein a maximum thickness in the second direction (X-direction, direction left to right) of the first insulating part 54 between the first side surface portion (left side of 24) of the gate electrode 24 and the side surface (right side) of the mesa part (portion of 10/12/14 between trenches 36; ¶ 0037) is less than a maximum thickness in the second direction (X-direction) of the first insulating part 54 between the bottom portion (bottom portion of 24) of the gate electrode 24 and the side surface (right side) of the mesa part. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gangi to provide the recited maximum thickness relationship for the purpose of providing an insulating part and gate electrode in an alternative, art-recognized configuration, as exemplified by Viswanathan (Fig. 4G). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B. Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. CANDICE Y. CHAN Examiner Art Unit 2813 26 June 2026 /STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Read full office action

Prosecution Timeline

Feb 21, 2024
Application Filed
Jul 07, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
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SEMICONDUCTOR DEVICES HAVING WETTABLE FLANKS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
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Patent 12641780
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Patent 12635188
SEMICONDUCTOR DEVICE INCLUDING MEMORY STRUCTURE ARRANGED ADJACENT TO PLANAR GATE STRUCTURE
3y 8m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
92%
With Interview (+19.2%)
3y 3m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 551 resolved cases by this examiner. Grant probability derived from career allowance rate.

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