Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 21, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Amendment filed January 2, 2026 has been entered. Claim(s) 1-20 remain pending in the application. Claims 1, 6, 7, 9, 10, 18 & 20 have been amended. Applicant’s amendments to the Claims have overcome each and every objection previously set forth in the Non-Final Office Action mailed October 2, 2025, hereafter referred to as the Non-Final Office Action.
Response to Arguments
Applicant's arguments filed January 2, 2026 have been entered and fully considered but they are not persuasive. Applicant in their submitted response has presented the argument, please refer to pgs. 11-13 of applicant’s remarks, that the prior art references in amended independent claim(s) 1 & 18, under U.S.C. § 103, Aaltonen in view of Matsuo, and amended independent claim 20, under U.S.C. § 103, Aaltonen in view of Matsuo, and further in view of Hughes, do not teach all the limitations currently recited in amended independent claims 1, 18 & 20. Applicant’s argument in summary is that the mapping of Aaltonen’s elements, in view of the mapping of Matsuo’s elements, are inconsistent with the plain language of claim 1, similarly amended into claims 18 & 20. The argument represented by the applicant has been reproduced below:
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The examiner respectfully disagrees based off what the applicant has disclosed within their own application. The applicant presents the argument that the prior art references, individually or in combination do no teach, disclose, and/or suggest, amended independent claim(s) 1, 18 & 20 language, “-1/2 * M2 + 9/2*M - 3 secondary switches selectively coupling the second terminal of each of the M capacitive elements to the first and second inputs of the first circuit;”. The switch formula (-1/2 * M^2 + 9/2*M -3), amended into independent claim(s) 1, 18 & 20, was evaluated by plugging in the integer established in claim 1, 18 & 20’s first element stating “M capacitive elements, wherein M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential;”. Due to M=2 (two feedback capacitors per channel in Aaltonen), the formula evaluates to: -1/2(4) + 9/2(2) – 3 = -2 + 9 – 3 = 4. A POSITA would utilize this exact switch count to achieve the differential sampling recited in amended independent claim(s) 1, 18 & 20. Aaltonen, discloses the switch formula topology that has been amended into independent claim(s) 1, 18 & 20, in Figure 3, that illustrates the secondary switches, exactly 4 switches associated with coupling the double feedback switch capacitors per differential channel in the Cfb network to the inputs/outputs per differential branch (controlled by clock phases c and xc). The secondary switches (driven by the mutually inverted clock phases c and xc) actively function to selectively couple the second terminals of the M capacitive elements to the feedback capacitors Cfb to the inverting and non-inverting inputs of the differential operational amplifier, which acts as the first circuit. Aaltonen’s switched capacitor (SC) derivator uses a fully differential architecture, therefore the switching network can route the stored charges to both the first and second inputs of the amplifier during the successive clock cycles to measure the peak-to-peak difference. Further, Aaltonen discloses a control circuit (clock circuitry 23 comprising a PLL) configured to receive a first clock signal and implement successive cycles. Teaching that taking two samples for each input cycle (M = 2 periods) by clocking the network in mutually inverted clock phases.
The examiner respectfully disagrees with the applicant’s contentions that Aaltonen, in view of Matsuo, fail to disclose, teach, and/or suggest individually or in combination, the above stated amendment(s) in independent claims 1 & 18, or that Aaltonen, in view of Matsuo, and further in view of Hughes, fail to disclose, teach, and/or suggest individually or in combination, the above stated amendment(s) in independent claim 20. The prior art references further disclose the additional limitations that have been amended and included in independent claims 1, 18 & 20, and meet these requirements. Therefore, the applicant’s arguments are unconvincing and the rejections of amended independent claims 1, 18 & 20, and dependent claims 2-17 & 19, which depend from and incorporate the limitations of amended independent claims 1 & 18, are respectively maintained. Updated rejections based on amended features follow.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 18 & 20, recite “-1/2 * M2 + 9/2 * M – 3 secondary switches selectively coupling the second terminal of each of the M capacitive elements to the first and second inputs of the first circuit” in ll. 11-12, without prior disclosure in the specification, therefore considered new matter. The topology formula would be difficult to determine from the specification material provided and there is no indication of “selectively coupling the second terminal of each of the M capacitive elements to the first and second inputs of the first circuit”. Claims 2-17 are rejected by virtue of dependency on claim 1, and claim 19 is rejected by virtue of dependency on claim 18, which do not rectify the defect.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-11, & 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Aaltonen (US 2015/0226556 A1, Pub. Date Aug. 13, 2025, hereinafter Aaltonen), in view of Matsuo (US 5986599, Pat. Date Nov. 16, 1999, hereinafter Matsuo).
Regarding independent claim 1, Aaltonen, teaches:
A derivative measurement circuit, comprising (Fig. 3; [0031] & [0043]: reference describes a “switched capacitor derivator” which is a circuit that measures the derivative of an input signal):
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M capacitive elements (Figs. 3 & 5; [0043] & [Claim 14]: the SC derivator includes input capacitances Cin, in a typical differential SC circuit, one terminal of the capacitors is connected to a reference potential (e.g., analog ground or a common-mode voltage, uses input capacitors for signal sampling), the feedback capacitors Cfb also serve as storage elements), wherein M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential (Figs. 3 & 5; [0043] & [Claim 14]: in the differential configuration, the input capacitors Cin are connected to the input voltages, feedback capacitors Cfb and the amplifier’s operation imply a ground or common-mode reference at the amplifier inputs, the “zeroing switches” reset the feedback capacitors to a reference potential, Fig. 3 illustrates the multiple Cfb capacitors, which are configured with terminals to selectively connect to ground (a reference potential) via the indicated switches. Further, architecture is defined where M = 2 (two feedback capacitors per differential channel));
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M primary switches coupling a second terminal of each of the M capacitive elements to a first node configured to receive a first voltage determined by a voltage at a second input of the measurement circuit coupled with the first node (Fig. 3; [0031] & [0043]: switches (controlled/labeled by clock phases C and XC), that couple the feedback capacitors Cfb to the input nodes of the operational amplifier. The first node of the claim maps to the input nodes of the op-amp, which receive a voltage determined by the measurement circuit’s inputs (Vi1 and Vi2) passing through the input capacitors Cin);
a first circuit configured to deliver, at a first output of the measurement circuit, a second voltage indicating a value of a voltage difference between first and second inputs of the first circuit (Figs. 2-3; [0032] & [0043]: the SC derivator is a differential amplifier OPA1 and (SAMPLING AMP), that produces an output voltage, Vo1 and Vo2, based on the difference between charges sampled on its inputs, “…voltages Vi1, Vi2 to input capacitances Cin”, identifies the first circuit as a differential amplifier, the outputs of the amplifier (Vo1 and Vo2) deliver the second voltage, which represents the sampled, peak-to-peak different (voltage difference) of the input signals);
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-1/2 * M2 + 9/2 * M – 3 secondary switches selectively coupling the second terminal of each of the M capacitive elements to the first and second inputs of the first circuit (Fig. 3; illustrates the secondary switches, which are driven by the mutually inverted clock phases c and xc, actively function to selectively couple the terminals of the feedback capacitors Cfb to the inverting and non-inverting inputs of the differential amplifier, which acts as the first circuit); and
a control circuit configured to (Figs. 2-3 & 5; [0030] & [0042]-[0043]):
receive a first clock signal available at a third input of the measurement circuit (Figs. 2-3 & 5; [0030] &[0042]-[0043]: operation is controlled by clock signals C and XC, which are derived from a master clock signal synchronized with the resonator’s oscillation frequency f0, “The SC derivator circuit may be clocked at the same frequency as the input signal coming into the sampling amplifier from the HPF…”);
implement successive cycles each corresponding to a succession of M periods of a second clock signal determined by the first clock signal (Figs. 2-3 & 5; [0042]-[0043]: circuit operates in successive cycles corresponding to the sampling period of the input signal, each cycle involving two non-overlapping clock phases C and XC, which can be considered M=2 periods, and the “clock circuitry (23)” and “START UNIT (500)” generate and use clock signals (C, XC, CLK SIGNALS) to control the sampling amplifier switches in successive cycles and periods); and
the first voltage is memorized on one of the M capacitive elements (Fig. 3; [0043]: during each clock phase C or XC, the input voltage is sampled onto the input capacitors Cin and the charge is transferred to the feedback capacitors Cfb, “memorizing” the voltage); and
the first input of the first circuit receives a voltage memorized at a first instant on one of the M capacitive elements and the second input of the first circuit receives a voltage representative of the first voltage at a second instant different from the first instant (Fig. 3; [0043]: samples the input at two different instants (e.g., the positive peak and the negative peak, corresponding to phases C and XC, the differential amplifier then outputs a voltage proportional to the difference between the two sampled values, which is the peak-to-peak voltage, a derivate measurement, “When edges of clock signals C and XC occur at peak values of the input signal, the output will produce the peak-to-peak value of the input signal”, directly describes receiving voltages from two different instants and producing an output indicative of their difference, “two samples are thus taken for each input signal cycle, so that each wave is sampled from peak-to-peak”, one input gets a stored sample, while the other one gets a different sample).
Aaltonen, is silent in regard to:
control the switches such that, at each period of each cycle:
However, Matsuo, further teaches:
control the switches such that, at each period of each cycle ([Col. 2, ll. 48-54], [Col. 4, ll. 45-67], [Col. 5, ll. 1-53], [Claim 1], [Claim 9] & [Claim 12]: outlines a sampling operation where charge is stored by capacitors, followed by a comparison operation triggered by inverted clock phases, acting as the “period of each cycle”):
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate multi-instant clocking scheme of Matsuo into the switched-capacitor derivator of Aaltonen. The motivation to combine would be to ensure precise, phase-controlled charge storage and transfer within the differential measurements circuit, minimizing signal loss and improving the accuracy of the peak-to-peak amplitude extraction. The combination represents the predictable use of prior art elements, according to their established functions and methods, to yield an expected result in switched-capacitor signal processing (KSR).
Regarding dependent claim 3, Aaltonen, teaches:
The derivative measurement circuit according to claim 1 (Fig. 3; [0031] & [0043]), wherein:
M is equal to 2 (Fig. 3; [0043]: circuit is designed with two sets of feedback switches capacitors CFb, that allow the circuit to operate in two “mutually inverted phases C and XC,” taking two samples per signal period, and mentions that two samples are taken for each input signal cycle); and
Aaltonen, is silent in regard to:
the control circuit is configured to control the switches such that, at each cycle:
that of the M capacitive elements on which the first voltage is memorized is
different at each period of the cycle, and
at each period of the cycle, the second input of the first circuit receives a voltage
across the terminals of one of the M capacitive elements other than the one on which the memorization is done at this cycle, and the first input of the first circuit receives a voltage across the other of the M capacitive elements.
However, Matsuo, further teaches:
the control circuit is configured to control the switches such that, at each cycle:
that of the M capacitive elements on which the first voltage is memorized is
different at each period of the cycle ([Col. 1, ll. 44-55], [Col. 2, ll. 16-30 & 48-64], [Col. 9, ll. 54-65], [Col. 18, Claim 9, ll. 50-55], & [Col. 19, Claim 10, ll. 48-58]: describes a “sampling operation” where charges are stored in the sampling use capacitor elements CS1 and CS2, followed by a “comparison operation”, where the timing of these operations is controlled by the control circuit TIMGEN, the circuit’s switches (S1, S3, S5, S7, etc.) are operated by various clock signals (SC K D2, XSCK, XSCKD1), where the process is “repeatedly performed” to “sequentially deciding its bits from the most significant bit to the least significant bit”, showing a cyclic process different capacitors are used in sequence, demonstrating that the specific capacitors being charged change with each decision period.), and
at each period of the cycle, the second input of the first circuit receives a voltage across the terminals of one of the M capacitive elements other than the one on which the memorization is done at this cycle, and the first input of the first circuit receives a voltage across the other of the M capacitive elements ([Col. 2, ll. 55-67], [Col. 8, ll. 65-67] & [Col. 9, ll. 1-21]: details a “comparison operation” that follows the “sampling operation, during the comparison phase, the switches are reconfigured so that the voltages across the capacitors are used to generate differential inputs V+ and V- for the operation amplifier, the capacitors (e.g., CS1 and CS2) are charged during the sampling operation, and the stored charge is used to determine the voltages V+ and V- in the comparison operation, which is a form of reading a memorized voltage from a capacitor while another capacitor may be used for a new sampling or comparison).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the control circuit configured to control the switches such that, at each cycle that of the M capacitive elements on which the first voltage is memorized is different at each period of the cycle, and at each period of the cycle, the second input of the first circuit receives a voltage across the terminals of one of the M capacitive elements other than the one on which the memorization is done at this cycle, and the first input of the first circuit receives a voltage across the other of the M capacitive elements, of Matsuo to Aaltonen. In order to attain and improve, by combination, taking the general concept from Aaltonen (switched-capacitor derivator using two capacitors) and apply the detailed circuit and control principles from Matsuo (charging capacitors in one phase, using the stored voltage in another, all controlled by a central circuit) to implement a working derivative measurement circuit, Matsuo also shows a successive approximation type ADC, where the use of multiple capacitors and sequential sampling/comparison of Matsuo, making the two-capacitor configuration of Aaltonen a direct and obvious application to these principles, according to known methods and yielding predictable results (KSR).
Regarding dependent claim 4, Aaltonen, teaches:
The derivative measurement circuit according to claim 1 (Fig. 3; [0031] & [0043]), wherein:
Aaltonen, is silent in regard to:
M is equal to 3; and
the control circuit is configured to control the switches such that, at each cycle:
that of the M capacitive elements on which the first voltage is memorized is
different at each period of the cycle, and
at each period of the cycle, the first input of the first circuit receives a voltage across the terminals of one of the M capacitive elements other than the one on which the memorization is done at this cycle, and the second input of the first circuit receives a voltage across of another of the M capacitive elements other than the one on which the memorization is done at this period.
However, Matsuo, further teaches:
M is equal to 3 (Fig. 10; [Col. 1, ll. 44-55], [Col. 2, ll. 48-64], [Col. 10, ll. 55-67], [Col. 11, ll. 1-17]: describes an “M number of capacitors” used in a charge redistribution type ADC, where “M” is the number of bits in the digital code, provides an example of a four-bit parallel ADC using 15 voltage division resistors and 14 comparators); and
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the control circuit is configured to control the switches such that, at each cycle ([Col. 1, ll. 44-55], [Col. 2, ll. 16-30 & 48-64], [Col. 4, ll. 45-67], & [Col. 5, ll. 1-34]: teaches the control circuit TIMGEN controls the “conductive states” of switches to perform a “repeatedly performed” “sampling operation and comparison operation”):
that of the M capacitive elements on which the first voltage is memorized is
different at each period of the cycle ([Col. 11, ll. 18-28 & 48-59], [Col. 12, ll. 9-22]: patent teaches a successive approximation type ADC that sequentially decides bits, process requires that the capacitor configuration changes for each bit decision, thus the memorization of a reference voltage is done at a different set of capacitors each period), and
at each period of the cycle, the first input of the first circuit receives a voltage across the terminals of one of the M capacitive elements other than the one on which the memorization is done at this cycle, and the second input of the first circuit receives a voltage across of another of the M capacitive elements other than the one on which the memorization is done at this period ([Col. 2, ll. 16-30 & 48-67], [Col. 3, ll. 1-10], & [Col. 11, ll. 18-28 & 48-59]: teaches the comparison operation of the ADC, the voltages of the connection nodes, which are determined by the stored charges of the capacitor elements, are input to the operation amplifier, the control circuit sets the switches to provide these voltages from the capacitors to the amplifier’s inputs).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate M is equal to 3 and the control circuit is configured to control the switches such that, at each cycle, that of the M capacitive elements on which the first voltage is memorized is different at each period of the cycle, and at each period of the cycle, the first input of the first circuit receives a voltage across the terminals of one of the M capacitive elements other than the one on which the memorization is done at this cycle, and the second input of the first circuit receives a voltage across of another of the M capacitive elements other than the one on which the memorization is done at this period, of Matsuo to Aaltonen. In order to attain and improve, by combination, taking the general concept from Aaltonen (switched-capacitor derivator using two capacitors) and implement the detailed, modular architecture taught in Matsuo, where the selection of M=3 is not a novel step, but a routine design choice to create a three-bit derivative measurement, that is common practice in ADC design to balance resolution, speed, and complexity, the result yielding a predictable combination of existing technologies, according to known methods and yielding predictable results (KSR).
Regarding dependent claim 5, Aaltonen, teaches:
The derivative measurement circuit according to claim 1 (Fig. 3; [0031] & [0043]), wherein:
Aaltonen, is silent in regard to:
M is equal to 3; and
each cycle corresponds to a succession of first, second and third periods of the second clock signal; and
the control circuit is configured to control the switches such that:
at each first period, the first voltage is memorized on a first element and the first and second inputs of the first circuit receive voltages of third and second elements, respectively,
at each second period, the first voltage is memorized on the second element and the first and second inputs of the first circuit receive voltages of the first and third elements, respectively, and
at each third period, the first voltage is memorized on the third element and the first and second inputs of the first circuit receive voltages of the second and first elements, respectively.
However, Matsuo, further teaches:
M is equal to 3 (Fig. 10; [Col. 1, ll. 44-55], [Col. 2, ll. 48-67], [Col. 10, ll. 55-67], [Col. 11, ll. 1-17]: describes an “M number of capacitors” used in a charge redistribution type ADC, where “M” is the number of bits in the digital code, provides an example of a four-bit parallel ADC using 15 voltage division resistors and 14 comparators); and
each cycle corresponds to a succession of first, second and third periods of the second clock signal ([Col. 1, ll. 44-55], [Col. 2, ll. 48-67], [Col. 10, ll. 55-67], [Col. 11, ll. 1-17]: describes a cycle with distinct, non-overlapping phases (e.g., sampling phase, comparison phase) controlled by a clock signal); and
the control circuit is configured to control the switches such that (Fig. 7; [Col. 8, ll. 33-41 & 65-67], [Col. 9, ll. 17-21]:provides specific control logic for a 3-phase rotation, a control circuit (clock signal generator and switch controllers) is configured to manage the switches (S1, S2, S5, S6, S7, S8, S11, S12) across different phases to route signals to different capacitor elements (C1, C2, C3, C4), and also demonstrates a control circuit configuring switches to connect different nodes (and different capacitor elements) during different clock periods):
at each first period, the first voltage is memorized on a first element and the first and second inputs of the first circuit receive voltages of third and second elements, respectively ([Col. 2, ll. 16-30 & 48-64], [Col. 5, ll. 35-53], & [Col. 9, ll. 10-65]:discloses a method where, during different clock periods, voltages are memorized on different capacitor elements (C1, C2, C3, C4), and the inputs to the comparator (the “first circuit”) are connected to different combinations of these elements to cancel out offset and low-frequency noise (e.g., the DC component Vc), teaches a “comparison operation” where the voltages of the connection nodes, which are a result of the stored charge of the capacitors, are input to the operational amplifier, and in the “charge redistribution type” ADC, capacitors are charged with a reference voltage and then used as inputs to the comparator, memorized voltage being received at the inputs of the circuit, providing a complete rotation that averages out errors associated with each element),
at each second period, the first voltage is memorized on the second element and the first and second inputs of the first circuit receive voltages of the first and third elements ([Col. 2, ll. 16-30 & 48-64], [Col. 5, ll. 35-53], & [Col. 9, ll. 10-65]: same reasoning for the full 3-phase rotation sequence), respectively, and
at each third period, the first voltage is memorized on the third element and the first and second inputs of the first circuit receive voltages of the second and first elements ([Col. 2, ll. 16-30 & 48-64], [Col. 5, ll. 35-53], & [Col. 9, ll. 10-65]: same reasoning for the full 3-phase rotation sequence), respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate M is equal to 3 each cycle corresponds to a succession of first, second and third periods of the second clock signal and the control circuit is configured to control the switches such that, at each second period, the first voltage is memorized on the second element and the first and second inputs of the first circuit receive voltages of the first and third elements, and at each third period, the first voltage is memorized on the third element and the first and second inputs of the first circuit receive voltages of the second and first elements, of Matsuo to Aaltonen. In order to attain and improve, by combination, where the problem of offset and noise in high-precision SC circuits in Aaltonen is well-known, in order to improve the accuracy of Aaltonen’s derivator, would look to known error-cancelling techniques in the field, Matsuo provides a well-known technique (correlated double sampling/input offset cancellation, using a rotating multi—phase memory scheme and applying it to the derivator circuit of Aaltonen would cancel errors, leading to the claimed 3-phase sequence, where the specific choice of M=3 represents a routine design choice within the known technique, (e.g., 2-phase, 3-phase, 4-phase chopping) to achieve a desired level of error suppression, the result yielding a predictable combination of existing technologies, according to known methods and yielding predictable results (KSR).
Regarding dependent claim 6, Aaltonen, teaches:
The derivative measurement circuit according to claim 5 (Fig. 3; [0031] & [0043]),
Aaltonen, is silent in regard to:
wherein the primary switches comprise a first switch coupling the second terminal of the first element with the first node, a second primary switch coupling the second terminal of the second element with the first node, and a third primary switch coupling the second terminal of the third element with the first node.
However, Matsuo, further teaches:
wherein the primary switches comprise a first switch coupling the second terminal of the first element with the first node (Fig. 7; [Col. 5, ll. 35-53], [Col. 8, ll. 65-67], [Col. 9, ll. 1-21], & [Col. 19, Claim 10, ll. 48-58]: teaches a circuit where multiple sampling elements (CS1/CS2) are connected to a common node (ND3/ND4) via individual, dedicated switches (SW2/SW4), illustrating the switch-and-element arrangement, and describes switches 2 and 4 individually coupling elements CS1 and CS2 to nodes ND1 and ND2 (are analogous to the “first node”)), a second primary switch coupling the second terminal of the second element with the first node (Fig. 7; [Col. 5, ll. 35-53], [Col. 8, ll. 65-67], [Col. 9, ll. 1-21], & [Col. 19, Claim 10, ll. 48-58]: refer to rational for first switch above, where switch 4 is the “second switch” that couples the “second element” CS2 to its corresponding node ND2), and a third primary switch coupling the second terminal of the third element with the first node (Figs. 7 & 10; [Col. 5, ll. 35-53], [Col. 10, ll. 55-67], [Col. 11, ll. 1-28, 31-42, 48-67], [Col. 12, ll. 1-22], & [Col. 19, Claim 10, ll. 48-58]: provides a clear teaching of circuits with more than two capacitor elements, each connected to a common node via its own dedicated switch, Fig. 10 shows a bank of capacitors C00 to C0m-1, each connected to a common node via individual switches SW00 to SW0m-1, teaches the use of a “third switch” for a ”third element”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the primary switches comprise a first switch coupling the second terminal of the first element with the first node, a second primary switch coupling the second terminal of the second element with the first node, and a third primary switch coupling the second terminal of the third element with the first node, of Matsuo to Aaltonen. In order to attain and improve, by combination, where Aaltonen discloses a derivative measurement circuit (SC derivator) used for precise amplitude detection in a MEMS drive loop, shows a circuit in Fig. 3 that inherently uses switches to connect capacitive elements to a common node (the op-amp input), and Matsuo in the analogous field of sampled-data analog circuits (ADCs) teaches the architectural feature of connecting multiple capacitor elements to a common node via individual dedicated switches in Figs. 7 ( two elements) & 10 ( generalizes “M” number of elements, making it clear that it is a scalable circuit design technique). By combining the function provided by Matsuo’s architecture of precise control and sampling of multiple capacitive elements, Aaltonen’s SC derivator would achieve its goal of “high precision amplitude demodulation”, rendering the “primary switches” arrangement obvious, since it applies to a known design pattern from one area of sampled-data circuit design, Matsuo’s ADC, to another related area, Aaltonen’s derivative measurement circuit, according to known methods and yielding predictable results (KSR).
Regarding dependent claim 7, Aaltonen, teaches:
The derivative measurement circuit according to claim 5 (Fig. 3; [0031] & [0043]), wherein the control circuit is configured to:
Aaltonen, is silent in regard to:
at each first period, keep open the second and third primary switches and switch the first primary switch to an ON state;
at each second period, keep open the third and first primary switches and switch the second primary switch to the ON state; and
at each third period, keep open the second and first primary switches and switch the third primary switch to the ON state.
However, Matsuo, further teaches:
at each first period, keep open the second and third primary switches and switch the first primary switch to an ON state (Figs. 3 & 4; [Col. 2, ll. 16-67], [Col. 3, ll. 1-10], [Col. 10, ll. 55-67], [Col. 11, ll. 3-59], [Col. 12, ll. 9-22]: describes the specific switch states during the sampling operation (first period), switches 2, 4, 5, 6 are ON (analogous to “first switch”) while switches 1, 3, 7, 8 are OFF (analogous to “second and third switches”));
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at each second period, keep open the third and first primary switches and switch the second primary switch to the ON state (Figs. 3 & 4; [Col. 2, ll. 16-67], [Col. 3, ll. 1-10], [Col. 10, ll. 55-67], [Col. 11, ll. 3-59], [Col. 12, ll. 9-22]: describes the specific switch states during the comparison operation (second period), switches 1, 2, 7, 8 are ON (analogous to “second switch”), while the others are OFF); and
at each third period, keep open the second and first primary switches and switch the third primary switch to the ON state (Figs. 3 & 4; [Col. 2, ll. 16-67], [Col. 3, ll. 1-10], [Col. 10, ll. 55-67], [Col. 11, ll. 3-59], [Col. 12, ll. 9-22]: describes the specific switch states during the sampling operation, switches 2, 4, 5, 6 are ON (analogous to “third switch”) while switches 1, 3, 7, 8 are OFF (analogous to “second and first switches”), also Fig. 4 further illustrates and teaches, clock signals (SCK, XSCK, SCKD1, SCKD2, etc.) are generated to be non-overlapping, ensuring that the switch states change in distinct periods to prevent signal contention and errors).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate at each first period, keep open the second and third primary switches and switch the first primary switch to an ON state, at each second period, keep open the third and first primary switches and switch the second primary switch to the ON state, and at each third period, keep open the second and first primary switches and switch the third primary switch to the ON state, of Matsuo to Aaltonen. In order to attain and improve, by combination, to configure the control circuit of the derivative measurement circuit (SC derivator) of Aaltonen to operate its switches in the specific, non-overlapping multi-period sequence as taught by Matsuo, where Aaltonen discloses a derivative measurement circuit that requires switched capacitor operation using clock signals. Matsuo solves the problem of accurately controlling switches in sampled data systems by teaching a method of operating switches in distinct, non-overlapping periods (e.g., sampling and comparison) to prevent signal corruption and ensure precise operation, and Aaltonen’s SC derivator would inherently depend on non-overlapping switch control to avoid short-circuiting the input signal and to correctly sample the peak-to-peak voltage. Therefore Matsuo’s switch control methodology, implemented to the claimed three-period sequence, would be a predictable extension of the two-period control system disclosed by Matsuo, that would accommodate a more complex sampling algorithm or a different circuit topology within the derivative measurement circuit, according to known methods, with predictable use of prior art elements, and yielding predictable results (KSR).
Regarding dependent claim 8, Aaltonen, teaches:
The derivative measurement circuit according to claim 5 (Fig. 3; [0031] & [0043]), wherein each memorization of the first voltage on the respective capacitive element ([0043]: teaches the memorization of a voltage as a charge on a capacitive element during a specific phase of a clock signal) for example less than or equal to one period of the second clock signal ([0043]: teaches sampling occurs within a portion of the overall signal period, specifically during the clock phases C and SX, the active time of these phases is less than the period of the clock signal that generates them), preferably equal to half a period of the second clock signal ([0043]: teaches a direct and precise method of a memorization duration equal to half the period of the fundamental clock f0 or equivalently, one full period of the 2* f0 clock).
Aaltonen, is silent in regard to:
has a same duration,
However, Matsuo, further teaches:
has a same duration (Figs. 4 & 9 [Col. 2, ll. 16-67], [Col. 3, ll. 1-20], [Col. 8, ll. 49-67], [Col. 9, ll. 1-67], & [Col. 10, ll. 1-54]: the standard operation of switched-capacitor circuits, as illustrated in the clock waveforms of Figs. 4 & 9, relies on clock phases with the same duration to ensure predictable and balanced circuit operation),
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a same duration, of Matsuo to Aaltonen. In order to attain and improve, by combination, to implement the derivative measurement circuit of Aaltonen to use a standard, two-phase non-overlapping clock scheme of Matsuo, where each memorization event has the same duration, which is typically half the period of the controlling clock signal, to achieve stable and accurate operation, where a conventional design choice for a known circuit would be a simple application, according to known methods, and yield predictable results (KSR).
Regarding dependent claim 9, Aaltonen, teaches:
The derivative measurement circuit according to claim 5 (Fig. 3; [0031] & [0043]), wherein the second switches comprise:
first and second secondary switches coupling the second terminal of the first element respectively with the first and second inputs of the first circuit (Fig.3; [0043]: figure illustrates the first input capacitor Cin (“first element”) is connected via one switch (controlled by phase C) to one input (Vi1) and via another switch (controlled by phase XC) to the other input (Vi2), which are the claimed “first and second switches” );
third and fourth secondary switches coupling the second terminal of the second element respectively with the first and second inputs of the first circuit (Fig. 3; [0043]: describes “doubling the feedback switched capacitors” and the figure further illustrates a symmetrical structure, a second Cin capacitor (“second element”) is connected via a third switch (C) to Vi2 and a fourth switch (XC) to Vi1, which are the claimed “third and fourth switches”); and
Aaltonen, is silent in regard to:
fifth and sixth secondary switches coupling the second terminal of the third element respectively with the first and second inputs of the first circuit.
However, Matsuo, further teaches:
fifth and sixth secondary switches coupling the second terminal of the third element respectively with the first and second inputs of the first circuit (Fig. 7; [Col. 10, ll. 55-67], [Col. 11, ll. 1-42]: figured illustrates a bank of multiple capacitors (C00, C01, etc., representing a “third element” and beyond), each capacitor in the bank is connected to the two differential input lines (analogous to the “first and second inputs of the first circuit”) via its own set of switches (e.g., SW0m-1 and SW1m-1), and teaches the claimed “fifth and sixth second switches” for a third element).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate fifth and sixth secondary switches coupling the second terminal of the third element respectively with the first and second inputs of the first circuit, of Matsuo to Aaltonen. In order to attain and improve, by combination, to implement the teaching of Matsuo into the derivator circuit of Aaltonen, adding a third capacitor with its corresponding fifth and sixth switches, improving increased charge storage, programmability, or component matching, to achieve stable and accurate operation, in analog and mixed-signal circuit design, and yield predictable results (KSR).
Regarding dependent claim 10, Aaltonen, teaches:
The derivative measurement circuit according to claim 9 (Fig. 3; [0031]-[0032] & [0043]), wherein the control circuit is configured to (Fig. 3; [0031]-[0032], [0043], & [0048]-[0052]: describes a “sampling amplifier (SAMPLING AMP) which “includes a switched capacitor derivator”, this circuit is “clocked at the same frequency as the input signal…but two amplitude samples may be received per one signal period…”, establishes the use of a control circuit generating non-overlapping clock phases to control switches in a derivator/sampling circuit, also describes a “start-up state” with “multiple stages”, teaching a control circuit that operates in more than two distinct periods or stages (e.g., first start-up stage, second start-up stage, third start-up stage/normal operation), providing rationale for third period with a distinct configuration to perform a specific function in sequence):
Aaltonen, is silent in regard to:
at each first period, switch the fifth and fourth secondary switches to an ON state and keep open the other secondary switches;
at each second period, switch the first and sixth secondary switches to the ON state and keep open the other secondary switches; and
at each third period, switch the third and second secondary switches to the ON state and keep open the other secondary switches.
However, Matsuo, further teaches:
at each first period, switch the fifth and fourth secondary switches to an ON state and keep open the other secondary switches (Figs. 3 & 4; [Col. 2, ll. 16-67], [Col. 3, ll. 1-10], [Col. 10, ll. 55-67], [Col. 11, ll. 3-59], [Col. 12, ll. 9-22]: sampling operation, maps to the “first period”, describes the specific switch states during the sampling operation, with the exact pattern, a specific set of switches 2, 4, 5, 6 are ON (analogous to “first and fourth second switches”) while switches 1, 3, 7, 8 are OFF (analogous to “other secondary switches”, the numbering convention may differ, but the pattern of controlling specific groups is identical);
at each second period, switch the first and sixth secondary switches to the ON state and keep open the other secondary switches (Figs. 3 & 4; [Col. 2, ll. 16-67], [Col. 3, ll. 1-10], [Col. 10, ll. 55-67], [Col. 11, ll. 3-59], [Col. 12, ll. 9-22]: describes the specific switch states during the comparison operation (second period), switches 1 and 3 (analogous to “first and sixth second switches”) are ON, while the previously ON switches (2, 3, 4, 6) are now OFF, the numbering convention may differ, but the pattern of controlling specific groups is identical); and
at each third period, switch the third and second secondary switches to the ON state and keep open the other secondary switches (Figs. 3-4 & 9; [Col. 2, ll. 16-67], [Col. 3, ll. 1-10], [Col. 10, ll. 55-67], [Col. 11, ll. 3-59], [Col. 12, ll. 9-22]: waveforms in Figs. 4 & 9 and the detailed timing description show that the clock signals (SCK, XSCK, SCKD1, SCKD2, etc.) create multiple, non-overlapping phases (e.g., sampling, comparison, and pre-charge/transfer phases within the overall cycle, the numbering convention may differ, but the pattern of controlling specific groups is identical, describes the specific switch states during the sampling operation, switches 2, 4, 5, 6 are ON (analogous to “third and second secondary switches”) while switches 1, 3, 7, 8 are OFF (analogous to “other secondary switches”)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate at each first period, switch the fifth and fourth secondary switches to an ON state and keep open the other secondary switches, at each second period, switch the first and sixth secondary switches to the ON state and keep open the other secondary switches, and at each third period, switch the third and second secondary switches to the ON state and keep open the other secondary switches, of Matsuo to Aaltonen. In order to attain and improve, by combination, to configure the control circuit of the derivative measurement circuit (SC derivator) using a control circuit with multiple clock phases (C/XC) to control switches with more than two operational periods/stages of Aaltonen to operate its switches in the specific, non-overlapping multi-period sequence with a voltage comparator, as taught by Matsuo. Aaltonen discloses a derivative measurement circuit that requires a switched capacitor operation using clock signals, Matsuo solves the problem of accurately controlling switches in sampled data systems by teaching a method of operating switches in distinct, non-overlapping periods (e.g., sampling and comparison) to prevent signal corruption and ensure precise operation, where a control circuit is configured to switch specific groups of switches to an ON state during one period (sampling) and a completely different group ON during a second period (comparison). Aaltonen’s SC derivator would inherently depend on non-overlapping switch control to avoid short-circuiting the input signal and to correctly sample the peak-to-peak voltage, therefore Matsuo’s switch control methodology, implemented to the claimed three-period sequence, would be a predictable extension of the two-period control system disclosed by Matsuo, that would accommodate a more complex sampling algorithm or a different circuit topology within the derivative measurement circuit, according to known methods, where the specific pattern of which switches are ON/OFF in the third period, would be a matter of routine design choice to achieve the desired circuit function (e.g., derivative measurement), with predictable use of prior art elements, and yielding a high expectation of predictable results (KSR).
Regarding dependent claim 11, Aaltonen, teaches:
The derivative measurement circuit according to claim 1 (Fig. 3; [0031] & [0043]-[0044]: figure illustrates the switched capacitor derivator circuit, which performs a derivative function to extract amplitude), wherein the measurement circuit further comprises
Aaltonen, is silent in regard to:
a first smoothing capacitive element connected between the first input of the first circuit and the first input of the measurement circuit
and a second smoothing capacitive element connected between the second input of the first circuit and the first input of the measurement circuit.
However, Matsuo, further teaches:
a first smoothing capacitive element connected between the first input of the first circuit and the first input of the measurement circuit (Figs. 3 & 7; [Abstract], [Col. 1, ll. 11-23], [Col. 2, ll. 1-64], [Col. 9, ll. 10-16], [Col. 10, ll. 8-12], [Col. 11, ll. 43-59]: Fig. 3 illustrates a “sampling use capacitor element CS1” connected between the input node ND1 and the amplifier input V-, Fig. 7 illustrates capacitor C1 connected between node ND3 (input to the first circuit/comparator) and ground, functioning to store the DC component and smooth the operational point)
and a second smoothing capacitive element connected between the second input of the first circuit and the first input of the measurement circuit (Figs. 3 & 7; [Abstract], [Col. 1, ll. 11-23], [Col. 2, ll. 1-64], [Col. 9, ll. 10-16], [Col. 10, ll. 8-12], [Col. 11, ll. 43-59]: describes the “…DC component VC is supplied to the capacitor elements C1 and C2 connected to the nodes ND3 and ND4…”, Fig. 7 illustrates the symmetrical capacitor C2 connected between node ND4 (second input to the first circuit/comparator) and ground, performing the identical smoothing function as C1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a first smoothing capacitive element connected between the first input of the first circuit and the first input of the measurement circuit and a second smoothing capacitive element connected between the second input of the first circuit and the first input of the measurement circuit, of Matsuo to Aaltonen. In order to attain and improve, by combination, where the derivative measurement circuit of Aaltonen is susceptible to offsets and flicker noise, Matsuo addresses this problem, teaching that connecting capacitive elements C1/C2 to the inputs of a circuit (a comparator, a type of measurement circuit) to store the DC component of the input results in a significant reduction in the fluctuation of the operation points, smoothing the DC operating point. Incorporating Matsuo’s teaching into the derivative measurement circuit of Aaltonen, to improve its stability and accuracy, according to known methods, with predictable use of prior art elements, and yielding a high expectation of predictable results (KSR).
Regarding dependent claim 13, Aaltonen, teaches:
The derivative measurement circuit according to claim 1 (Fig. 3; [0030]-[0031], [0037], [0039], & [0043]-[0044]: circuit includes a “sampling amplifier (SAMPLING AMP)” which is described as a “switched capacitor derivator” circuit, figured provides the detailed circuit diagram of the derivator), wherein the measurement circuit further comprises:
Aaltonen, is silent in regard to:
a first comparator configured to compare the second voltage with a positive threshold voltage provided by the control circuit, and to provide a first binary signal indicating if the second voltage is greater than the positive threshold voltage; and/or
a second comparator configured to compare the second voltage with a negative threshold voltage provided by the control circuit, and to provide a second binary signal indicating if the second voltage is lower than the positive threshold voltage.
However, Matsuo, further teaches:
a first comparator configured to compare the second voltage with a positive threshold voltage provided by the control circuit, and to provide a first binary signal indicating if the second voltage is greater than the positive threshold voltage (Figs. 1 & 7; [Abstract], [Col. 1, ll. 11-67], [Col. 2, ll. 1-67], [Col 3, ll. 1-67], [Col. 16, Claim 1, ll. 50-67], [Col. 17, Claim 1, ll. 1-37]: describes a voltage comparator circuit that compares an input voltage to a reference voltage (“positive threshold”) and provides a binary output signal (D/XD), Fig. 7 details the circuitry to achieve this, the operational amplifier 10 can be considered a comparator, or its output is latched by latch circuit 20 to produce a binary output D/XD); and/or
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a second comparator configured to compare the second voltage with a negative threshold voltage provided by the control circuit, and to provide a second binary signal indicating if the second voltage is lower than the positive threshold voltage (Figs. 1 & 7; [Abstract], [Col. 1, ll. 7-67], [Col. 2, ll. 1-67], [Col 3, ll. 1-67], [Col. 20, Claim 12, ll. 13-67], [Col. 21, ll.1-11], & [Col. 22, ll. 1-10]: describes a parallel ADC with multiple comparators COMP1 to COMP14, each receiving different reference threshold voltage pairs (VRTn/VRBn), to generate a set of binary signals, conventional to use multiple comparators, each set to a different threshold (e.g., a positive and a negative one in a window comparator configuration), teaches using multiple comparators with different thresholds).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a first comparator configured to compare the second voltage with a positive threshold voltage provided by the control circuit, and to provide a first binary signal indicating if the second voltage is greater than the positive threshold voltage and a second comparator configured to compare the second voltage with a negative threshold voltage provided by the control circuit, and to provide a second binary signal indicating if the second voltage is lower than the positive threshold voltage, of Matsuo to Aaltonen. In order to attain and improve, by combination, where Aaltonen discloses a derivative measurement circuit (SC derivator) and a system that uses multiple comparators (COMP1/COMP2) to generate clock signals. Matsuo provides a detailed teaching of voltage comparator circuits, their structure, and their function of comparing an input voltage to a reference threshold to generate a binary output, further establishes the common practice of using a plurality of comparators in a single system, each with its own reference point. By combining, connecting one or more dedicated comparators of Matsuo to the output of the derivator circuit of Aaltonen to monitor its voltage level against predetermined positive and negative thresholds, generating binary flags for a control circuit, according to known methods, with predictable use of prior art elements, and yielding a high expectation of predictable results (KSR).
Regarding dependent claim 14, Aaltonen, teaches:
The derivative measurement circuit according to claim 13 (Fig. 3; [0030]-[0031], [0036]-[0037], [0039], [0043]-[0044], & [0074]: circuit includes a “sampling amplifier (SAMPLING AMP)” which is described as a “switched capacitor derivator” circuit, figured provides the detailed circuit diagram of the derivator), wherein:
the measurement circuit comprises the first comparator ([0030]-[0032] & [0038]-[0043]: includes comparators as part of its measurement and clock generation circuitry, COMP1 is used to generate a clock signal from the amplified resonator signal); and
Aaltonen, is silent in regard to:
the control circuit is configured to adapt a value of the positive threshold voltage as a function of a value of the first voltage.
However, Matsuo, further teaches:
the control circuit is configured to adapt a value of the positive threshold voltage as a function of a value of the first voltage ([Abstract], [Col. 8, ll. 7-67], [Col. 9, ll. 1-67]: describes technique for adapting the effective comparison threshold, the comparator uses a network of capacitors (C1, C2, C3, C4) to store the DC component of the input signal VC and the reference voltage Vref, during the comparison phase, the voltages on these capacitors are combined, setting the comparison threshold as a function of the stored input and reference voltages, Equations (7) and (8) show that the final compared voltages (V-/V+) are functions of both the input signal and the stored DC component/reference, meaning the threshold for comparison is adapted by the input).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the control circuit configured to adapt a value of the positive threshold voltage as a function of a value of the first voltage, of Matsuo to Aaltonen. In order to attain and improve, by combination, where Aaltonen discloses a derivative measurement circuit (SC derivator) with a comparator and a control system that adapts operational parameters (DC bias voltages) based on a measured signal. Matsuo provides a well-known circuit implementation for a voltage comparator where the threshold is dynamically set and adapted based on input voltages, where the dynamic threshold adaptation would improve comparator accuracy and stability. The combination leads to a derivative measurement circuit where a control circuit adapts to a positive threshold voltage as a function of a first voltage, according to known methods, with predictable use of prior art elements, and yielding a high expectation of predictable results (KSR).
Regarding dependent claim 15, Aaltonen, teaches:
The derivative measurement circuit according to claim 14 (Figs. 2 & 4-5; [0030]-[0031], [0036]-[0037], [0039], [0043]-[0044], [0048], & [0074]: circuit includes a “sampling amplifier (SAMPLING AMP)” which is described as a “switched capacitor derivator” circuit, figured provides the detailed circuit diagram of the derivator), wherein the control circuit (Figs. 2 & 4-5; [0030]-[0031], [0036]-[0037], [0039], [0043]-[0044], [0048], & [0074]: circuit includes a “sampling amplifier (SAMPLING AMP)” which is described as a “switched capacitor derivator” circuit, figured provides the detailed circuit diagram of the derivator, the “start-up circuitry” 25 and the precise “controller circuit” (START UNIT 500) constitute the control circuit, the sampling amplifier (SAMPLING AMP) and the drive loop 22 that processes the resonator signal can be considered part of the derivative measurement circuitry) is configured to decrease the value of the positive threshold voltage ([0061]-[0065]; discloses a control circuit that changes its threshold, uses hysteresis, where a higher threshold is used to end the start-up state and a lower threshold is used to re-initiate it, also states that the threshold can be altered by changing component values such as capacitance ratios) when the first voltage is positive and increases (Figs. 4-5; [0048]-[0049], [0054], [0060]-[0061]: the “first voltage” corresponds to the amplitude measurement signal (e.g., Vi2-Vi1 in Fig. 5) from the MEMS resonator, during the start-up state, this signal is positive and increases exponentially (as shown in the DRV curve of Fig. 4) until it crosses a threshold, the control circuit (START UNIT 500) is configured to sample and monitor the increased voltage).
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Regarding dependent claim 16, Aaltonen, teaches:
The derivative measurement circuit according to claim 13 (Figs. 2-3; [0028]-[0039], [0043]-[0044], & [0074]: circuit includes a “sampling amplifier (SAMPLING AMP)” which is described as a “switched capacitor derivator” circuit, figured provides the detailed circuit diagram of the derivator, entire circuitry 20 constitutes a measurement and control circuit for MEMS resonator, includes the detection, amplification, and feedback loops that measure the resonator’s signal and derive control signals from it), wherein:
the measurement circuit comprises the second comparator ([0028]-[0039] & [0059]-[0060]: entire circuitry 20 constitutes a measurement and control circuit for MEMS resonator, includes the detection, amplification, and feedback loops that measure the resonator’s signal and derive control signals from it, discloses a second comparator COMP2 within a measurement circuit); and
the control circuit is configured to adapt a value of the negative threshold voltage ([0060]-[0065]: discloses control circuit (START-UP MODE CTRL, CLK REF CTROL) is configured to adapt a threshold (for hysteresis) by changing component ratios (e.g., capacitors C1/C2), demonstrates the principle of an adaptively controlled threshold in a similar circuit)
Aaltonen, is silent in regard to:
as a function of a value of the first voltage.
However, Matsuo, further teaches:
as a function of a value of the first voltage ([Abstract], [Col. 8, ll. 7-67], [Col. 9, ll. 1-67]: describes technique for adapting the effective comparison threshold, the comparator uses a network of capacitors (C1, C2, C3, C4) to store the DC component of the input signal VC and the reference voltage Vref, during the comparison phase, the voltages on these capacitors are combined, setting the comparison threshold as a function of the stored input and reference voltages, Equations (7) and (8) show that the final compared voltages (V-/V+) are functions of both the input signal and the stored DC component/reference, meaning the threshold for comparison is adapted by the input, also discloses using the value of the DC component VC (a first voltage) to set the charge on capacitors C1 and C2, where the operation and the effective threshold of the comparator are a direct function of the voltage VC).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a function of a value of the first voltage, of Matsuo to Aaltonen. In order to attain and improve, by combination, where Aaltonen discloses a derivative measurement circuit (MEMS drive loop) with a second comparator (COMP2) and a control circuit that adapts a threshold voltage, and Matsuo provides a detailed disclosure of comparator circuits where the effective comparison threshold is adapted as a function of a first voltage (the DC component VC) through the biasing of capacitors. Implementing the well-known technique from Matsuo, using a first voltage to bias a comparator’s threshold-defining components into the control circuit of Aaltonen to achieve the specific function of adapting the negative threshold voltage as a function of the first voltage, where threshold adaptation would improve comparator accuracy and stability, according to known methods, with predictable use of prior art elements, and yielding a high expectation of predictable results (KSR).
Regarding dependent claim 17, Aaltonen, teaches:
The derivative measurement circuit according to claim 16 (Figs. 2-3; [0028]-[0039], [0043]-[0044], & [0074]: circuit includes a “sampling amplifier (SAMPLING AMP)” which is described as a “switched capacitor derivator” circuit, figured provides the detailed circuit diagram of the derivator, entire circuitry 20 constitutes a measurement and control circuit for MEMS resonator, includes the detection, amplification, and feedback loops that measure the resonator’s signal and derive control signals from it), wherein the control circuit is configured ([0031] & [0048]: describes foundational context of a measurement and control circuit within a resonator system, describing the sampling amplifier providing “high precision amplitude demodulation” for the amplitude control and start-up circuitry)
Aaltonen, is silent in regard to:
to decrease an absolute value of the negative threshold voltage when the first voltage is negative and decreases.
However, Matsuo, further teaches:
to decrease an absolute value of the negative threshold voltage ([Col. 9, ll. 1-67], [Col. 10, ll. 1-67], [Col. 11, ll. 1-67], [Col. 12, ll. 1-65]: invention designed to compensate for fluctuations in the DC component VC of the input signal, where the purpose of the added capacitor elements (C1, C2, C3, C4) and switching network (switches 7, 8, 11, 12) is to adjust the effective threshold or operating point of the comparator to prevent errors, when the DC component VC changes, the circuit effectively “decreases the absolute value” of the impact the DC shift has on the comparator’s decision point/threshold) when the first voltage is negative and decreases (Fig. 9A; [Col. 9, ll. 1-67], [Col. 10, ll. 1-67], [Col. 11, ll. 1-67], [Col. 12, ll. 1-65]: operates with a “first voltage” that can be negative and decrease, the input signals AIN and XAIN are differential (one is the inverse of the other), when one is positive, the other is negative, the circuit’s operation is designed to handle the scenario where these input voltages, and particularly their DC component VC, change, also provides an example that describes a condition where the input signal’s DC level is not at the expected midpoint, one side of the differential pair is at a more negative potential relative to the reference, and this “negative voltage” can “decrease” further, circuit is designed to compensate for this scenario).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate to decrease an absolute value of the negative threshold voltage when the first voltage is negative and decreases, of Matsuo to Aaltonen. In order to attain and improve, by combination/integration, of the specific threshold-adjustment technique of Matsuo into the general control circuit of Aaltonen to improve the system’s robustness and precision when handling signals that are “negative and decreasing”, to solve the common problem. Improving the maintaining of a stable and accurate control when dealing with fluctuating input signals, according to known methods, with predictable use of prior art elements, and yielding a high expectation of predictable results (KSR).
Regarding independent claim 18, Aaltonen, teaches:
A derivative measurement circuit (Fig. 3; [0031] & [0043]: reference describes a “switched capacitor derivator” which is a circuit that measures the derivative of an input signal), comprising:
M capacitive elements (Figs. 3 & 5; [0043] & [Claim 14]: the SC derivator includes input capacitances Cin, in a typical differential SC circuit, one terminal of the capacitors is connected to a reference potential (e.g., analog ground or a common-mode voltage, uses input capacitors for signal sampling), the feedback capacitors Cfb also serve as storage elements), wherein M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential (Figs. 3 & 5; [0043] & [Claim 14]: in the differential configuration, the input capacitors Cin are connected to the input voltages, feedback capacitors Cfb and the amplifier’s operation imply a ground or common-mode reference at the amplifier inputs, the “zeroing switches” reset the feedback capacitors to a reference potential, Fig. 3 illustrates the multiple Cfb capacitors, which are configured with terminals to selectively connect to ground (a reference potential) via the indicated switches. Further, architecture is defined where M = 2 (two feedback capacitors per differential channel));
M primary switches coupling a second terminal of each of the M capacitive elements to a first node configured to receive a first voltage determined by a voltage at a second input of the measurement circuit coupled with the first node (Fig. 3; [0031] & [0043]: switches (controlled/labeled by clock phases C and XC) that couple/connect the feedback capacitors Cfb to the input nodes of the operational amplifier. The first node of the claim maps to the input nodes of the op-amp, which receives a voltage determined by the measurement circuit’s inputs Vi1 and Vi2, passing through the input capacitors Cin);
a first circuit configured to deliver, at a first output of the measurement circuit, a second voltage indicating a value of a voltage difference between first and second inputs of the first circuit (Figs. 2-3; [0032] & [0043]: the SC derivator is a differential amplifier OPA1 and (SAMPLING AMP), that produces an output voltage, Vo1 and Vo2, based on the difference between charges sampled on its inputs, “…voltages Vi1, Vi2 to input capacitances Cin”, identifies the first circuit as a differential amplifier, the outputs of the amplifier (Vo1 and Vo2) deliver the second voltage, which represents the sampled, peak-to-peak different (voltage difference) of the input signals);
-1/2 * M2 + 9/2 * M – 3 secondary switches selectively coupling the second terminal of each of the M capacitive elements to the first and second inputs of the first circuit (Fig. 3; illustrates the secondary switches, which are driven by the mutually inverted clock phases c and xc, actively function to selectively couple the terminals of the feedback capacitors Cfb to the inverting and non-inverting inputs of the differential amplifier, which acts as the first circuit);
a control circuit configured to (Figs. 2-3 & 5; [0030] & [0042]-[0043]):
receive a first clock signal available at a third input of the measurement circuit (Figs. 2-3 & 5; [0030] & [0042]-[0043]: operation is controlled by clock signals C and XC, which are derived from a master clock signal synchronized with the resonator’s oscillation frequency f0, “The SC derivator circuit may be clocked at the same frequency as the input signal coming into the sampling amplifier from the HPF…”);
implement successive cycles each corresponding to a succession of M periods of a second clock signal determined by the first clock signal (Figs. 2-3 & 5; [0042]-[0043]: circuit operates in successive cycles corresponding to the sampling period of the input signal, each cycle involving two non-overlapping clock phases C and XC, which can be considered M=2 periods, and the “clock circuitry (23)” and “START UNIT (500)” generate and use clock signals (C, XC, CLK SIGNALS) to control the sampling amplifier switches in successive cycles and periods); and
the first voltage is memorized on one of the M capacitive elements (Fig. 3; [0043]: during each clock phase C or XC, the input voltage is sampled onto the input capacitors Cin and the charge is transferred to the feedback capacitors Cfb, “memorizing” the voltage); and
the first input of the first circuit receives a voltage memorized at a first instant on one of the M capacitive elements and the second input of the first circuit receives a voltage representative of the first voltage at a second instant different from the first instant (Fig. 3; [0043]: samples the input at two different instants (e.g., the positive peak and the negative peak, corresponding to phases C and XC, the differential amplifier then outputs a voltage proportional to the difference between the two sampled values, which is the peak-to-peak voltage, a derivate measurement, “When edges of clock signals C and XC occur at peak values of the input signal, the output will produce the peak-to-peak value of the input signal”, directly describes receiving voltages from two different instants and producing an output indicative of their difference, “two samples are thus taken for each input signal cycle, so that each wave is sampled from peak-to-peak”, one input gets a stored sample, while the other one gets a different sample);
Aaltonen, is silent in regard to:
control the switches such that, at each period of each cycle:
a first comparator configured to compare the second voltage with a positive threshold voltage provided by the control circuit, and to provide a first binary signal indicating if the second voltage is greater than the positive threshold voltage; and
a second comparator configured to compare the second voltage with a negative threshold voltage provided by the control circuit, and to provide a second binary signal indicating if the second voltage is lower than the positive threshold voltage.
However, Matsuo, further teaches:
control the switches such that, at each period of each cycle ([Col. 2, ll. 48-54], [Col. 4, ll. 45-67], [Col. 5, ll. 1-53], [Claim 1], [Claim 9] & [Claim 12]: outlines a sampling operation where charge is stored by capacitors, followed by a comparison operation triggered by inverted clock phases, acting as the “period of each cycle”):
a first comparator configured to compare the second voltage with a positive threshold voltage provided by the control circuit, and to provide a first binary signal indicating if the second voltage is greater than the positive threshold voltage (Figs. 1 & 7; [Abstract], [Col. 1, ll. 11-67], [Col. 2, ll. 1-67], [Col 3, ll. 1-67], [Col. 16, Claim 1, ll. 50-67], [Col. 17, Claim 1, ll. 1-37]: describes a voltage comparator circuit that compares an input voltage to a reference voltage (“positive threshold”) and provides a binary output signal (D/XD), Fig. 7 details the circuitry to achieve this, the operational amplifier 10 can be considered a comparator, or its output is latched by latch circuit 20 to produce a binary output D/XD); and
a second comparator configured to compare the second voltage with a negative threshold voltage provided by the control circuit, and to provide a second binary signal indicating if the second voltage is lower than the positive threshold voltage (Figs. 1 & 7; [Abstract], [Col. 1, ll. 7-67], [Col. 2, ll. 1-67], [Col 3, ll. 1-67], [Col. 20, Claim 12, ll. 13-67], [Col. 21, ll.1-11], & [Col. 22, ll. 1-10]: describes a parallel ADC with multiple comparators COMP1 to COMP14, each receiving different reference threshold voltage pairs (VRTn/VRBn), to generate a set of binary signals, conventional to use multiple comparators, each set to a different threshold (e.g., a positive and a negative one in a window comparator configuration), teaches using multiple comparators with different thresholds).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the multi-instant clocking scheme of Matsuo, controlling switches such that, at each period of each cycle, a first comparator configured to compare the second voltage with a positive threshold voltage provided by the control circuit, and to provide a first binary signal indicating if the second voltage is greater than the positive threshold voltage, and a second comparator configured to compare the second voltage with a negative threshold voltage provided by the control circuit, and to provide a second binary signal indicating if the second voltage is lower than the positive threshold voltage, of Matsuo to Aaltonen. In order to attain and improve, by combination, where Aaltonen discloses a derivative measurement circuit (SC derivator) and a system that uses multiple comparators (COMP1/COMP2) to generate clock signals, including a switched-capacitor sampling amplifier, a control clock, and comparator-based threshold detection with hysteresis. Matsuo teaches a well-known implementation of a switched-capacitor measurement circuit, detailing the use of M capacitors, switches, a differential amplifier, and a control circuit operating with a clock signal to perform sequential sampling and comparison, a core principal in analog-to-digital conversion, and provides a detailed teaching of voltage comparator circuits, their structure, and their function of comparing an input voltage to a reference threshold to generate a binary output, further establishes the common practice of using a plurality of comparators in a single system, each with its own reference point. Combining prior art reference elements, connecting one or more dedicated comparators of Matsuo to the output of the derivator circuit of Aaltonen to monitor its voltage level against predetermined positive and negative thresholds, generating binary flags for a control circuit, implementing the measurement and threshold detection functions required by Aaltonen using the precise switched-capacitor circuit architecture taught by Matsuo, where the use of a second comparator to establish a lower threshold for hysteresis is taught by both references. The motivation to combine would be to ensure precise, phase-controlled charge storage and transfer within the differential measurements circuit, minimizing signal loss and improving the accuracy of the peak-to-peak amplitude extraction, to create a robust, noise-resistant detection system, according to known methods, with predictable use of prior art elements, and yielding a high expectation of predictable results (KSR).
Regarding dependent claim 19, Aaltonen, teaches:
The derivative measurement circuit according to claim 18 (Fig. 3; [0031] & [0043]: reference describes a “switched capacitor derivator” which is a circuit that measures the derivative of an input signal), wherein the control circuit is configured to:
adapt a value of the negative threshold voltage as a function of a value of the first voltage ([0028]-[0039] & [0059]-[0065]: requires a lower, adaptive threshold for hysteresis (e.g., to prevent unnecessary restart), entire circuitry 20 constitutes a measurement and control circuit for MEMS resonator, includes the detection, amplification, and feedback loops that measure the resonator’s signal and derive control signals from it, discloses a second comparator COMP2 within a measurement circuit).
Aaltonen, is silent in regard to:
adapt a value of the positive threshold voltage as a function of a value of the first voltage; and
However, Matsuo, further teaches:
adapt a value of the positive threshold voltage as a function of a value of the first voltage ([Abstract], [Col. 8, ll. 7-67], [Col. 9, ll. 1-67]: teaches the measurement circuit to implement, by using capacitors C1/C2 to sample and store the DC component of the input signal VC, and the reference voltage Vref, during the comparison phase, the voltages on these capacitors are combined, setting the comparison threshold of the comparator circuit as a function of the stored input and reference voltages, Equations (7) and (8) show that the final compared voltages (V-/V+) are functions of both the input signal and the stored DC component/reference, meaning the threshold for comparison is adapted by the input); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate adapt a value of the positive threshold voltage as a function of a value of the first voltage, of Matsuo to Aaltonen. In order to attain and improve, by combination, where Aaltonen discloses a derivative measurement circuit (e.g., a drive loop circuit for a MEMS resonator) with a control circuit (e.g., the start-up controller 25, START-UP MODE CTRL, CLK REF CTRL) that adapts threshold voltages, teaches adapting a positive threshold (“stop threshold for ending the start-up state) and a negative threshold (“lower threshold” for reactivating the start-up state) as a function of the amplitude of a detected signal (e.g., the signal output of the HPF, which is a “first voltage”. Matsuo teaches a specific circuit for achieving the adaptive threshold, disclosing a voltage comparator that adapts comparison thresholds by sampling and storing the DC component VC of an input signal (“first voltage”) on capacitors C1/C2, setting both the positive and negative differential thresholds of the comparator as a function of the input signal’s DC value. The dynamic threshold adaptation would improve comparator accuracy and stability, where the combination leads to incorporating the DC-adaptive comparator circuit of Matsuo into the control circuit of Aaltonen, according to known methods, with predictable use of prior art elements, and yielding a high expectation of predictable results that adapts the values of its positive and negative threshold voltages as a function of a first voltage (KSR).
Claims 2, 12 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over Aaltonen, in view of Matsuo, and further in view of Hughes (EP 0416699 A1, Pat. Date Mar. 3, 1993).
Regarding dependent claim 2, Aaltonen, teaches:
The derivative measurement circuit according to claim 1 (Fig. 3; [0031] & [0043]), wherein:
Aaltonen, is silent in regard to:
M is equal to 1;
the first input of the first circuit is coupled to the first node; and
However, Matsuo, further teaches:
M is equal to 1 (Fig. 1; [Col. 1, ll. 44-55: describes multi-bit ADC’s, such as a “four-bit parallel type ADC”], referring to “M” as the number of bits in the converter, that can be simplified to a single-bit (M=1) circuit to achieve a simple on/off comparison);
the first input of the first circuit is coupled to the first node (Fig. 7; [Col. 10, ll. 27-31]: teaches coupling an input AIN to a first node ND1); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate M is equal to one, and the first input of the first circuit is coupled to the first node, of Matsuo to Aaltonen, in order to attain, by combination, a simplified multi-bit ADC disclosed in Matsuo to a single-bit (M=1), using the same core switched-capacitor comparator circuit from Aaltonen, and using a control circuit from Matsuo that manipulates switches to perform a sampling operation on a capacitive element, with a first input of the first circuit coupled to the first node, according to known methods and yielding predictable results (KSR).
Aaltonen, and Matsuo, are silent in regard to:
the control circuit is configured to control the switches such that, at each period of each cycle, the second input of the first circuit receives the voltage memorized on the capacitive element at this period.
However, Hughes, further teaches:
the control circuit is configured to control the switches such that, at each period of each cycle, the second input of the first circuit receives the voltage memorized on the capacitive element at this period (Figs. 2 & 3; [Pg. 3, ll. 53-58], [Pg. 4, ll. 1-10]: “During portion Φ2 of sampling period (n-1)…I1 = j + i(n-1), then during Φ1 of period n, this stored current (function the memorized gate voltage on capacitor C1) is used in the calculation for the first cell’s input, switches S1, S2, S3 are controlled by the clock phases to achieve this).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the control circuit is configured to control the switches such that, at each period of each cycle, the second input of the first circuit receives the voltage memorized on the capacitive element at this period, of Hughes to Aaltonen and Matsuo. In order to attain, by combination, combining the SC derivator structure from Aaltonen with the general clocking and sampling principles of Matsuo, with the knowledge from Hughes that differentiation and operation of controlling the switches to feed a memorized voltage back to an input at each period being a consequence of a difference-based (derivative) circuit in the sampled data domain, according to known methods and yielding predictable results (KSR).
Regarding dependent claim 12, Aaltonen, teaches:
The derivative measurement circuit according to claim 1 (Fig. 3; [0031], [0043]-[0044], & [0059]: figure illustrates the switched capacitor derivator circuit, which performs a derivative function to extract amplitude), wherein the measurement circuit further comprises
Aaltonen and Matsuo, are silent in regard to:
a second circuit coupling the second input of the measurement circuit with the first node, wherein the second circuit is a buffer circuit.
However, Hughes, further teaches:
a second circuit coupling the second input of the measurement circuit with the first node (Fig. 2; [Pg. 2, ll. 17-25 & 50-55], [Pg. 3, ll. 1-7], [Pg. 13, ll. 8-16]: shows the buffer circuits (current mirrors/memory cells) being used to couple inputs to internal nodes throughout all embodiments (e.g., the input current is coupled to the internal node of the first memory cell), Fig. 2 further illustrates the input 10 is coupled to the drain of T1 (input node of the memory cell/buffer)), wherein the second circuit is a buffer circuit (Fig. 2; [Pg. 2, ll. 17-25 & 50-55], [Pg. 3, ll. 1-7], [Pg. 13, ll. 8-16]: describes a basic current mirror/buffer cell, a current mirror is a classic buffer circuit in analog design, discloses and uses current mirrors as circuits, the memory cells, which are the core building blocks, are implemented using current mirrors that buffer the stored current to one or more outputs).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a second circuit coupling the second input of the measurement circuit with the first node, wherein the second circuit is a buffer circuit, of Hughes to Aaltonen and Matsuo. In order to attain, by combination, incorporating the use of a buffer circuit, such as the mirrors taught by Hughes, into the derivator circuit of Aaltonen. To improve performance characteristics such as impedance, output drive capability, signal integrity, which are well-known advantages of using buffer stages, where the buffer circuits (buffer mirrors) are fundamental building blocks for accurately sensing, storing, and reproducing currents in sampled-data systems, and would be directly applicable to the SC derivator of Aaltonen, rendering the combination obvious, to optimize Aaltonen’s circuit, using the well-known buffer structures of Hughes to couple signals within the derivator, according to known methods with predictable results through routine optimization (KSR).
Regarding independent claim 20, Aaltonen, teaches:
A derivative measurement circuit (Fig. 3; [0031] & [0043]: reference describes a “switched capacitor derivator” which is a circuit that measures the derivative of an input signal), comprising:
M capacitive elements (Figs. 3 & 5; [0043] & [Claim 14]: the SC derivator includes input capacitances Cin, in a typical differential SC circuit, one terminal of the capacitors is connected to a reference potential (e.g., analog ground or a common-mode voltage, uses input capacitors for signal sampling), the feedback capacitors Cfb also serve as storage elements), wherein M is an integer greater than or equal to 1, each having a first terminal connected to a first input of the measurement circuit configured to receive a reference potential (Figs. 3 & 5; [0043] & [Claim 14]: in the differential configuration, the input capacitors Cin are connected to the input voltages, feedback capacitors Cfb and the amplifier’s operation imply a ground or common-mode reference at the amplifier inputs, the “zeroing switches” reset the feedback capacitors to a reference potential, Fig. 3 illustrates the multiple Cfb capacitors, which are configured with terminals to selectively connect to ground (a reference potential) via the indicated switches. Further, architecture is defined where M = 2 (two feedback capacitors per differential channel));
M primary switches coupling a second terminal of each of the M capacitive elements to a first node configured to receive a first voltage determined by a voltage at a second input of the measurement circuit coupled with the first node (Fig. 3; [0031] & [0043]: switches (controlled/labeled by clock phases C and XC) that couple/connect the feedback capacitors Cfb to the input nodes of the operational amplifier. The first node of the claim maps to the input nodes of the op-amp, which receives a voltage determined by the measurement circuit’s inputs Vi1 and Vi2, passing through the input capacitors Cin);
a first circuit configured to deliver, at a first output of the measurement circuit, a second voltage indicating a value of a voltage difference between first and second inputs of the first circuit (Figs. 2-3; [0032] & [0043]: the SC derivator is a differential amplifier OPA1 and (SAMPLING AMP), that produces an output voltage, Vo1 and Vo2, based on the difference between charges sampled on its inputs, “…voltages Vi1, Vi2 to input capacitances Cin”, identifies the first circuit as a differential amplifier, the outputs of the amplifier (Vo1 and Vo2) deliver the second voltage, which represents the sampled, peak-to-peak different (voltage difference) of the input signals);
-1/2 * M2 + 9/2 * M – 3 secondary switches selectively coupling the second terminal of each of the M capacitive elements to the first and second inputs of the first circuit (Fig. 3; illustrates the secondary switches, which are driven by the mutually inverted clock phases c and xc, actively function to selectively couple the terminals of the feedback capacitors Cfb to the inverting and non-inverting inputs of the differential amplifier, which acts as the first circuit);
a control circuit configured to (Figs. 2-3 & 5; [0042]-[0043]):
receive a first clock signal available at a third input of the measurement circuit (Figs. 2-3 & 5; [0042]-[0043]: operation is controlled by clock signals C and XC, which are derived from a master clock signal synchronized with the resonator’s oscillation frequency f0, “The SC derivator circuit may be clocked at the same frequency as the input signal coming into the sampling amplifier from the HPF…”);
implement successive cycles each corresponding to a succession of M periods of a second clock signal determined by the first clock signal (Figs. 2-3 & 5; [0042]-[0043]: circuit operates in successive cycles corresponding to the sampling period of the input signal, each cycle involving two non-overlapping clock phases C and XC, which can be considered M=2 periods, and the “clock circuitry (23)” and “START UNIT (500)” generate and use clock signals (C, XC, CLK SIGNALS) to control the sampling amplifier switches in successive cycles and periods); and
the first voltage is memorized on one of the M capacitive elements (Fig. 3; [0043]: during each clock phase C or XC, the input voltage is sampled onto the input capacitors Cin and the charge is transferred to the feedback capacitors Cfb, “memorizing” the voltage); and
the first input of the first circuit receives a voltage memorized at a first instant on one of the M capacitive elements and the second input of the first circuit receives a voltage representative of the first voltage at a second instant different from the first instant (Fig. 3; [0043]: samples the input at two different instants (e.g., the positive peak and the negative peak, corresponding to phases C and XC, the differential amplifier then outputs a voltage proportional to the difference between the two sampled values, which is the peak-to-peak voltage, a derivate measurement, “When edges of clock signals C and XC occur at peak values of the input signal, the output will produce the peak-to-peak value of the input signal”, directly describes receiving voltages from two different instants and producing an output indicative of their difference, “two samples are thus taken for each input signal cycle, so that each wave is sampled from peak-to-peak”, one input gets a stored sample, while the other one gets a different sample);
Aaltonen, is silent in regard to:
control the switches such that, at each period of each cycle:
a first smoothing capacitive element connected between the first input of the first circuit and the first input of the measurement circuit and a second smoothing capacitive element connected between the second input of the first circuit and the first input of the measurement circuit; and
However, Matsuo, further teaches:
control the switches such that, at each period of each cycle ([Col. 2, ll. 48-54], [Col. 4, ll. 45-67], [Col. 5, ll. 1-53], [Claim 1], [Claim 9] & [Claim 12]: outlines a sampling operation where charge is stored by capacitors, followed by a comparison operation triggered by inverted clock phases, acting as the “period of each cycle”):
a first smoothing capacitive element connected between the first input of the first circuit and the first input of the measurement circuit (Figs. 3 & 7; [Abstract], [Col. 1, ll. 11-23], [Col. 2, ll. 1-64], [Col. 9, ll. 10-16], [Col. 10, ll. 8-12], [Col. 11, ll. 43-59]: Fig. 3 illustrates a “sampling use capacitor element CS1” connected between the input node ND1 and the amplifier input V-, Fig. 7 illustrates capacitor C1 connected between node ND3 (input to the first circuit/comparator) and ground, functioning to store the DC component and smooth the operational point)
and a second smoothing capacitive element connected between the second input of the first circuit and the first input of the measurement circuit (Figs. 3 & 7; [Abstract], [Col. 1, ll. 11-23], [Col. 2, ll. 1-64], [Col. 9, ll. 10-16], [Col. 10, ll. 8-12], [Col. 11, ll. 43-59]: describes the “…DC component VC is supplied to the capacitor elements C1 and C2 connected to the nodes ND3 and ND4…”, Fig. 7 illustrates the symmetrical capacitor C2 connected between node ND4 (second input to the first circuit/comparator) and ground, performing the identical smoothing function as C1); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the multi-instant clocking scheme, a first smoothing capacitive element connected between the first input of the first circuit and the first input of the measurement circuit and a second smoothing capacitive element connected between the second input of the first circuit and the first input of the measurement circuit of Matsuo to Aaltonen. In order to attain, by combination, a circuit with switches that couple capacitors to inputs of an amplifier/comparator, where the derivative measurement circuit of Aaltonen is susceptible to offsets and flicker noise. Matsuo addresses this problem, teaching that connecting capacitive elements C1/C2 to the inputs of a circuit (a comparator, a type of measurement circuit) to store the DC component of the input results in a significant reduction in the fluctuation of the operation points, smoothing the DC operating point. The motivation to combine would be to ensure precise, phase-controlled charge storage and transfer within the differential measurements circuit, minimizing signal loss and improving the accuracy of the peak-to-peak amplitude extraction. Furthermore, incorporating Matsuo’s teaching into the derivative measurement circuit of Aaltonen, would improve its stability and accuracy, according to known methods, with predictable use of prior art elements, and yielding a high expectation of predictable results (KSR).
Aaltonen, in combination with Matsuo, are silent in regard to:
a second circuit coupling the second input of the measurement circuit with the first node, wherein the second circuit is a buffer circuit.
However, Hughes, further teaches:
a second circuit coupling the second input of the measurement circuit with the first node (Fig. 2; [Pg. 2, ll. 17-25 & 50-55], [Pg. 3, ll. 1-7], [Pg. 13, ll. 8-16]: shows the buffer circuits (current mirrors/memory cells) being used to couple inputs to internal nodes throughout all embodiments (e.g., the input current is coupled to the internal node of the first memory cell, Fig. 2 further illustrates the input 10 is coupled to the drain of T1 (input node of the memory cell/buffer) ), wherein the second circuit is a buffer circuit (Fig. 2; [Pg. 2, ll. 17-25 & 50-55], [Pg. 3, ll. 1-7], [Pg. 13, ll. 8-16]: describes a basic current mirror/buffer cell, a current mirror is a classic buffer circuit in analog design, discloses and uses current mirrors as circuits, the memory cells, which are the core building blocks, are implemented using current mirrors that buffer the stored current to one or more outputs).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a second circuit coupling the second input of the measurement circuit with the first node, wherein the second circuit is a buffer circuit, of Hughes to Aaltonen and Matsuo. In order to attain, by combination, incorporating the use of a buffer circuit, such as the mirrors taught by Hughes, into the derivator circuit of Aaltonen to improve performance characteristics such as impedance, output drive capability, signal integrity, which are well-known advantages of using buffer stages, where the buffer circuits (buffer mirrors) are fundamental building blocks for accurately sensing, storing, and reproducing currents in sampled-data systems. Would be directly applicable to the SC derivator of Aaltonen, rendering the combination obvious, to optimize Aaltonen’s circuit, using the well-known buffer structures of Hughes to couple signals within the derivator, according to known methods with predictable results through routine optimization (KSR).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Del Cesta (US11831314B1) discloses ratiometric current or voltage source circuit with reduced temperature dependence. Ricca et al. (US2012/0007663A1) discloses integrated circuit with device for adjustment of the operating parameter value of an electronic circuit and with the same electronic circuit. Li et al. (US2014/0016358A1) discloses a voltage waveform detector, power controller and control method for switched-mode power supplies with primary-side control. Chang et al. (CN102111156A) discloses successive approximation register analog-to-digital conversion circuit for realizing minimal dynamic range. Tanimoto et al. (US4803382) discloses a voltage comparator circuit. Aaltonen (US9644961B2) discloses a circuit for a MEMS resonator. Zou (US12174227B2) discloses measuring voltage level of a voltage node utilizing a measurement integrated circuit. Thomas et al. (US10720840B2) discloses a DC-DC converter circuit with synchronization module and corresponding conversion method. Yue et al. (US20210067033A1) discloses differential sensing and maintenance of flying capacitor voltage in a switched-mode power supply circuit.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUGO NAVARRO/ Examiner, Art Unit 2858 March 24, 2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 3/31/2026
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