DETAILED ACTION
This Office Action is in response to the election filed on 28 July 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Species I (claims 1-12) in the reply filed on 28 July 2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hudson et al. (US 2022/0108651 A1; hereinafter Hudson).
In regards to claim 1, Hudson teaches, e.g. in figs. 4, a display device comprising:
a substrate (401) comprising:
a first well area (e.g. an instance of (380) in a pixel (433)); and
a second well area (e.g. another instance of (380) in another pixel (433)) spaced from the first well area (e.g. spaced the wells are in different respective pixels), the second well area having a voltage different from a voltage of the first well area (e.g. fig. 1B; [0036-0037]);
a first pixel circuit (e.g. fig. 1B; [0036]: e.g. (181a/182a1/182a2, etc.)) comprising:
a first transistor located on the first well area (figs. 4D; [0022]: multiple P-FETs on a single n-well); and
a second transistor located on the second well area (figs. 4D; [0022]: multiple P-FETs on a single n-well); and
a second pixel circuit (e.g. fig. 1B; [0036]: e.g. (181b/182b1/182b2, etc.)) comprising:
a third transistor located on the first well area (figs. 4D; [0022]: multiple P-FETs on a single n-well); and
a fourth transistor located on the second well area (figs. 4D; [0022]: multiple P-FETs on a single n-well).
In regards to claim 2, Hudson teaches the limitations discussed above in addressing claim 1. Hudson further teaches the limitations wherein the voltage of the first well area is higher than the voltage of the second well area ([0133]: bias).
In regards to claim 3, Hudson teaches the limitations discussed above in addressing claim 2. Hudson further teaches the limitations wherein the first well area has a rectangular shape (figs. 4), and the second well area comprises:
a first portion extending in a first direction, and spaced from the first well area in a second direction crossing the first direction (fig. 4A: e.g. a quadrant of (380));
a second portion extending in the second direction, and spaced from the first well area in the first direction (e.g. fig. 4A: e.g. a diagonally spaced quadrant of (380)); and
a third portion in contact with the first portion and the second portion (fig. 4A: e.g. a quadrant of (380) connected the first and second diagonally opposed quadrants of (380)).
In regards to claim 4, Hudson teaches the limitations discussed above in addressing claim 2. Hudson further teaches the limitations wherein each of the first transistor and the third transistor is a driving transistor of a corresponding pixel circuit (fig. 2E).
In regards to claim 5, Hudson teaches the limitations discussed above in addressing claim 2. Hudson further teaches the limitations further comprising a third pixel circuit comprising:
a fifth transistor located on the first well area (figs. 4D; [0022]: multiple P-FETs on a single n-well); and
a sixth transistor located on the second well area (figs. 4D; [0022]: multiple P-FETs on a single n-well).
In regards to claim 6, Hudson teaches the limitations discussed above in addressing claim 5. Hudson further teaches the limitations wherein the fifth transistor is a driving transistor (fig. 2E).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 7, Hudson teaches the limitations discussed above in addressing claims 1 and 2. Hudson does not appear to teach, alone or in combination with other art, the limitations wherein the substrate further comprises:
a third well area having a structure corresponding to a mirror image of that of the first well area with respect to a first direction, the third well area having a voltage equal to the voltage of the first well area; and
a fourth well area having a structure corresponding to a mirror image of that of the second well area with respect to the first direction, the fourth well area having a voltage equal to the voltage of the second well area, and
wherein the display device further comprises:
a fourth pixel circuit comprising a seventh transistor located on the third well area, and an eighth transistor located on the fourth well area;
a fifth pixel circuit comprising a ninth transistor located on the third well area, and a tenth transistor located on the fourth well area; and
a sixth pixel circuit comprising an eleventh transistor located on the third well area, and a twelfth transistor located on the fourth well area.
The claims of the application at hand that depend from the claims that are objected to as allowable are objected to as well because they respectively depend, directly or indirectly, from the objected to claims of the application at hand. Therefore, the dependent claims in question incorporate the allowable limitations of the claims from which they depend.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Primary Patent Examiner, Art Unit 2812
Prosecution Insights