DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Objections
The claim(s) is/are objected to because of the following informalities:
Claim 20: it appears that “sett” in line(s) 5 was meant to be -- set --.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10-11, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 2010/0074011 ‒hereinafter Kang).
Regarding claim 1, Kang discloses a method for operating a memory device, comprising:
setting (S50; fig. 4) an inhibit information (state A:1,B:0 is inverted to A:0,B:1 which provides inhibit information for memory cells; para 0072) to a first latch (latch 1411; fig. 2);
applying (S61; fig. 4) a first programming voltage to word lines of memory cells to program the memory cells (“operation for providing a program voltage to a wordline of the plurality of memory cells” para 0009, further para 0050);
inverting the inhibit information in the first latch (i.e. the inverted inhibit information in first latch 1411 is inverted a second time to A:1,B:0; para 0074) to form a first information (P2 verify read information S62; para 0074);
performing a verification operation (P3 verify read S63; fig. 4) on the memory cells, and storing a second information (P3 verify read information, para 0075) in the first latch (1411) according to the first information (i.e. P2 verify read information) and the verification operation (S63); and
after the verification operation (i.e. after P3 verify read S63), inverting the second information in the first latch (the second information in the first latch 1411 may be inverted in a repeated loop from S90; fig. 4).
Regarding claim 11, Kang discloses a memory device, comprising:
a memory array comprising memory cells (110; fig. 1); and
a peripheral circuit (120-180; fig. 1) coupled to the memory array (110), wherein the peripheral circuit is configured to:
set (S50; fig. 4) an inhibit information (state A:1,B:0 is inverted to A:0,B:1 which provides inhibit information for memory cells; para 0072) to a first latch (latch 1411; fig. 2);
apply (S61; fig. 4) a first programming voltage to word lines of memory cells to program the memory cells (“operation for providing a program voltage to a wordline of the plurality of memory cells” para 0009, further para 0050);
invert the inhibit information in the first latch (i.e. the inverted inhibit information in first latch 1411 is inverted a second time to A:1,B:0; para 0074) to form a first information (P2 verify read information S62; para 0074);
perform a verification operation (P3 verify read S63; fig. 4) on the memory cells, and store a second information (P3 verify read information, para 0075) in the first latch (1411) according to the first information (i.e. P2 verify read information) and the verification operation (S63); and
after the verification operation (i.e. after P3 verify read S63), invert the second information in the first latch (the second information in the first latch 1411 may be inverted in a repeated loop from S90; fig. 4).
Regarding claim 20, Kang discloses a memory system, comprising:
a memory device (100; fig. 1) comprising:
a memory array comprising memory cells (110; fig. 1); and
a peripheral circuit (120-180; fig. 1) coupled to the memory array (110), wherein the peripheral circuit is configured to:
sett (S50; fig. 4) an inhibit information (state A:1,B:0 is inverted to A:0,B:1 which provides inhibit information for memory cells; para 0072) to a first latch (latch 1411; fig. 2);
apply (S61; fig. 4) a first programming voltage to word lines of memory cells to program the memory cells (“operation for providing a program voltage to a wordline of the plurality of memory cells” para 0009, further para 0050);
invert the inhibit information in the first latch (i.e. the inverted inhibit information in first latch 1411 is inverted a second time to A:1,B:0; para 0074) to form a first information (P2 verify read information S62; para 0074);
perform a verification operation (P3 verify read S63; fig. 4) on the memory cells, and store a second information (P3 verify read information, para 0075) in the first latch (1411) according to the first information (i.e. P2 verify read information) and the verification operation (S63); and
after the verification operation (i.e. after P3 verify read S63), invert the second information in the first latch (the second information in the first latch 1411 may be inverted in a repeated loop from S90; fig. 4); and
a controller (210; fig. 12) coupled to the memory device (220; fig. 12, i.e. memory device 100).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 2010/0074011 ‒hereinafter Kang) in view of Shin et al. (US 2021/0072922 ‒hereinafter Shin).
Regarding claim 10, Kang does not expressly disclose the method, wherein one of the memory cells stores three logic bits.
Shin discloses one of the memory cells stores three logic bits (para 0066).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kang is modifiable as taught by Shin for the purpose of facilitating data accessing schemes to improve read command queues by allocating particular latches to a read operation (para 0118, 0147 of Shin), which is common and well known in the art for improving signal propagation delays.
Regarding claim 19, Kang does not expressly disclose the memory device, wherein the peripheral circuit is further configured to: setting lower page information of the memory cells to a third latch; setting middle page information of the memory cells to a fourth latch; and setting upper page information of the memory cells to a fifth latch; wherein the fifth latch comprises a cache latch.
Shin discloses setting lower page information of the memory cells to a third latch; setting middle page information of the memory cells to a fourth latch; and setting upper page information of the memory cells to a fifth latch (fig. 7); wherein the fifth latch comprises a cache latch (para 0147).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Kang is modifiable as taught by Shin for the purpose of facilitating data accessing schemes to improve read command queues by allocating particular latches to a read operation (para 0118, 0147 of Shin), which is common and well known in the art for improving signal propagation delays.
Allowable Subject Matter
Claim(s) 2-9 and 12-18 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
The allowable claims are supported in at least fig. 6 of the instant application.
Conclusion
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/UYEN SMET/
Primary Examiner, Art Unit 2824