Prosecution Insights
Last updated: October 02, 2026
Application No. 18/583,554

DISPLAY DEVICE

Final Rejection §102§103
Filed
Feb 21, 2024
Priority
Feb 28, 2023 — RE 10-2023-0027207
Examiner
JAHAN, BILKIS
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
821 granted / 926 resolved
+20.7% vs TC avg
Moderate +10% lift
Without
With
+10.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
26 currently pending
Career history
959
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
54.6%
+14.6% vs TC avg
§102
23.7%
-16.3% vs TC avg
§112
13.5%
-26.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 926 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Attorney Docket Number: F23-1035US001/590287.515 Filling Date: 02/21/24 Priority Date: 02/28/23 (not perfected) Inventor: Seo et al Examiner: Bilkis Jahan DETAILED ACTION In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 19, 21 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al (US 2014/0203301 A1). Regarding claim 19, Kim discloses a display device (Figs. 1-7), comprising: a substrate BS (Paras. 39, 40) including a display area DA (Para. 41) and a non-display area NDA (Para. 41) adjacent to the display area DA, the display area DA including a subpixel PE1, PE2 (Paras. 135, 141); a gate driving circuit GIC (Paras. 12, 42-43) disposed in the non-display area NDA, the gate driving circuit GIC generating a gate signal (inherent) and including a plurality of blocks CML, GIC (Para. 74); a first transistor GIC (left one) disposed in the gate driving circuit GIC and including a first active layer SM (Para. 87), a first gate electrode GE, a first source electrode SE, and a first drain electrode DE; and a second transistor GIC (right one) disposed in the gate driving circuit GIC and including a second active layer SM, a second gate electrode GE, a second source electrode SE, and a second drain electrode DE, wherein each of the first drain electrode DE, the second drain electrode DE, the first source electrode SE, and second source electrode SE extends along a first direction (X-direction, Fig. 6) , wherein the first drain electrode DE, G1C (left transistor) is positioned at one side of the first gate electrode GE in a second direction (Y-direction, consider thickness direction) crossing the first direction (X-direction), and the first source electrode SE is positioned at an opposite side of the first gate electrode GE in the second direction (Y-direction), wherein the second drain electrode DE , G1C (right transistor, Fig. 6) is positioned at one side of the second gate electrode GE in the second direction (Y-direction, thickness direction), and the second source electrode SE is positioned at an opposite side of the second gate electrode GE in the second direction (Y-direction), and wherein the gate driving circuit G1C (Fig. 1) is disposed at one side of the display area DA in the first direction (X-direction). Regarding claim 21, Kim further discloses the display device according to claim 19, further comprising: a signal line CML (Para. 74) disposed in the gate driving circuit GIC and extending along a second direction (Y-direction, Fig. 2); and a connection line PP (Para. 42) electrically connecting the signal line CML and the first drain electrode DE, wherein an extension direction of the connection line PP is parallel to the first direction (X-direction, slanted parallel). Regarding claim 22, Kim further discloses the display device according to claim 21, wherein the first direction (X-direction) is perpendicular to the second direction (Y-direction). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2014/0203301 A1). Regarding claim 20, Kim does not explicitly disclose the display device according to claim 19, further comprising a light emitting diode in the subpixel and over the substrate. However, Kim discloses color filter CF (Para. 58) in the subpixel PE1, PE2 and over the substrate BS. Therefore, it would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain the light from LED to the CR in order to get different color light from the LED device through CF (Para. 58). Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 2014/0203301 A1) in view of Cho et al (US 2019/0165079 A1). Regarding claim 23, Kim does not explicitly disclose the display device according to claim 19, wherein the first active layer includes a first channel region and first source and drain regions at both sides of the first channel region, and the second active layer includes a second channel region and second source and drain regions at both sides of the second channel region, wherein a first channel length direction is a direction connecting the first drain region and the first source region and passing through the first channel region, and a second channel length direction is a direction connecting the second drain region and the second source region and passing through the second channel region, and wherein the first channel length direction and the second channel length direction are in the second direction. However, Kim discloses two gate driving transistors with two sources, two drains and two gates G1C (Fig. 6). Also, Cho discloses a channel length direction 154d (middle, Fig. 2, Para. 65) is a direction connecting the drain region 154d (left portion) and the source region 154d (left portion) and passing through the first channel region 154d (middle). Cho teaches the above modification is used to reduce resistance of the device (Abstract). It would have been obvious to one of the ordinary skill of the art before the effective filling date of the claimed invention to obtain “a first channel length direction is a direction connecting the first drain region and the first source region and passing through the first channel region, and a second channel length direction is a direction connecting the second drain region and the second source region and passing through the second channel region, and wherein the first channel length direction and the second channel length direction are in the second direction” to reduce resistance of the device (Abstract). Response to Arguments Applicant's arguments filed 5/13/26 have been fully considered but they are not persuasive. Applicant’s argue: Kim fail to disclose the claimed feature of "wherein the first drain electrode is positioned at one side of the first gate electrode in a second direction crossing the first direction, and the first source electrode is positioned at an opposite side of the first gate electrode in the second direction, wherein the second drain electrode is positioned at one side of the second gate electrode in the second direction, and the second source electrode is positioned at an opposite side of the second gate electrode in the second direction, and wherein the gate driving circuit is disposed at one side of the display area in the first direction." Examiner Responds: However, the Examiner respectfully disagrees about the above arguments. The claim 19 does not explicitly define the definition of the 2nd direction. Examiner interprets the drain 2nd direction is the Y-direction which is thickness direction in Kim reference. Allowable Subject Matter Claims 1-15, 17 and 18 are allowed. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BILKIS JAHAN whose telephone number is (571)270-5022. The examiner can normally be reached Monday-Friday, 8:00 am-5 Pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon T Fletcher can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. BILKIS . JAHAN Primary Examiner Art Unit 2817 /BILKIS JAHAN/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Feb 21, 2024
Application Filed
Apr 07, 2026
Non-Final Rejection mailed — §102, §103
May 13, 2026
Response Filed
Aug 10, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+10.2%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 926 resolved cases by this examiner. Grant probability derived from career allowance rate.

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