DETAILED ACTION
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to Korean Patent Application No. 10-2023-0100704, filed on 8/1/2023.
Specification
The abstract of the disclosure is objected to because it does not conform to the content guidelines. Specifically, the abstract fails to adequately describe the invention, at least, because it does not mention the key power saving feature. Correction is required.
Claim Objections
The claims are objected to because of the following informalities:
In claim 12, it appears that the phrase ‘the power saving mode i’ should read ‘the power saving mode’.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Instances in the claims including a ‘management unit’ and a ‘tool control (TC) unit’ are interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
These claims recite a management unit and a tool control (TC) unit [claims 1 and 11] that invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. No hardware is disclosed to perform these functions; see MPEP 2181.
Claims depending on any of the above rejected claims are also rejected under 35 U.S.C. § 112 as they inherit all of the characteristics of the claim from which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
The claim limitations ‘a management unit’ and ‘a tool control (TC) unit’ [claims 1 and 11] are interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. No hardware is disclosed to perform these functions. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
In addition to the above:
With regard to claim 4, this claim recites ‘a laser irradiation unit configured to irradiate a laser’. However, it is clear from the specification/PGPub [0110] and corresponding claim 14 that the laser irradiates the product and not a laser and the claim language raises issues as to the intended meaning of the limitation and is thus indefinite.
With regard to claim 11, this claim recites ‘receiving, by a tool control (TC) unit, an output variable from the management unit to control the processor according to the output variable’ and it is not clear if the processor is actually controlled according to the output variable or if ‘to control’ is merely a statement of intended use.
With regard to claim 13, this claim recites ‘a temperature inside the chamber’ twice and then ‘the temperature’ and it is unclear if these are the same temperature or which of the previously recited temperatures corresponds to ‘the temperature’.
With regard to claim 14, this claim recites ‘a power level of the laser’ twice and then ‘the power level and it is unclear if these are the same power level or which of the previously recited power levels corresponds to ‘the power level.
Claims depending on any of the above rejected claims are also rejected under 35 U.S.C. § 112 as they inherit all of the characteristics of the claim from which they depend and none of the dependent claims provide a cure for the indefiniteness of claims from which they depend.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 10-11, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto et al. U.S. Patent Publication No. 20130178971 (hereinafter Hashimoto) in view of Quiros et al. U.S. Patent Publication No. 20220026884 (hereinafter Quiros).
Regarding claim 1, Hashimoto teaches an apparatus for manufacturing a display device [0001 — The present invention relates to a substrate processing apparatus for processing substrate and an electric power source management method of managing electric power supply therefor. Examples of substrates to be processed include semiconductor substrates, glass substrates for liquid crystal displays, glass substrates for plasma displays, substrates for FEDs (field emission displays; 0046, Fig. 4 — a substrate processing apparatus], the apparatus comprising:
a processor including a first process line including a plurality of first process devices configured to perform a first process, and a second process line including a plurality of second process devices configured to perform a second process [0041-0044, Figs. 2 and 4 — processing block 5 comprises a plurality of (for example, eight) processing units MPC… FIG. 4, a chemical supply unit CC1 at one side supplies chemical liquids to four processing units MPC 1 to 4, and a chemical supply unit CC2 at another side supplies chemical liquids to four processing units MPC 5 to 8; 0068 — Chemical liquid processing, rinse processing, and dry processing are sequentially carried out in the processing units MPC 1 to 4. (1-4, 2-4, 3-4, 4-4)]; and
a controller configured to control the processor, wherein each of the plurality of first process devices and the plurality of second process devices is configured to operate in a power saving mode [0050, Fig. 4 — main controller 6 comprises a CPU (central processing unit) 23, a memory device 24, and a scheduler 25, which functions through execution of programs stored in the memory device 24 by the CPU 23. The scheduler 25 includes a counter 26 that counts number of times of substrate processing by each of the processing unit MPC. The scheduler 25 prepares a time chart representing an operation scheme for the plurality of units based on a production information in a manner such that all of the steps that is to be carried out by the plurality of units according to the processing details included in the processing informations, is completed by the end time limit. And the main controller 6, by controlling a plurality of ON/OFF switching devices according to time chart, makes a plurality of unit U operate by supplying electric power thereto.; 0015 — It is possible to further decrease consumption of electric power because a number of chemical liquid supply units in a non-operation condition is at a maximum], and
the controller includes:
a management unit configured to generate an input variable including a target number of products to be processed during a predefined time duration in the first process line, a target number of products to be processed during the predefined time duration in the second process line, a number of the plurality of first process devices, a number of the plurality of second process devices [0050, Fig. 4 — main controller 6 comprises a CPU (central processing unit) 23, a memory device 24, and a scheduler 25, which functions through execution of programs stored in the memory device 24 by the CPU 23. The scheduler 25 includes a counter 26 that counts number of times of substrate processing by each of the processing unit MPC. The scheduler 25 prepares a time chart representing an operation scheme for the plurality of units based on a production information in a manner such that all of the steps that is to be carried out by the plurality of units according to the processing details included in the processing informations, is completed by the end time limit. And the main controller 6, by controlling a plurality of ON/OFF switching devices according to time chart, makes a plurality of unit U operate by supplying electric power thereto — the figures show the number of sheets/products and start/end times and the number of devices];
a scheduler configured to receive the input variable from the management unit and output an output variable to the management unit [0050, Fig. 4 — main controller 6 comprises a CPU (central processing unit) 23, a memory device 24, and a scheduler 25, which functions through execution of programs stored in the memory device 24 by the CPU 23. The scheduler 25 includes a counter 26 that counts number of times of substrate processing by each of the processing unit MPC. The scheduler 25 prepares a time chart representing an operation scheme for the plurality of units based on a production information in a manner such that all of the steps that is to be carried out by the plurality of units according to the processing details included in the processing informations, is completed by the end time limit. And the main controller 6, by controlling a plurality of ON/OFF switching devices according to time chart, makes a plurality of unit U operate by supplying electric power thereto]; and
a tool control (TC) unit configured to receive the output variable from the management unit and control the processor according to the output variable, wherein the output variable includes information about a power saving process device operating in a power saving mode among the plurality of first process devices and the plurality of second process devices, a power saving start time of the power saving process device, and a power saving end time of the power saving process device [0047-0050, Figs. 4-9 — By being controlled by the main controller 6, the ON/OFF switching device 22 switches between ON state and OFF state. Each of the unit U is supplied with electric power when corresponding ON/OFF switching device 22 is ON state… main controller 6 comprises a CPU (central processing unit) 23, a memory device 24, and a scheduler 25, which functions through execution of programs stored in the memory device 24 by the CPU 23. The scheduler 25 includes a counter 26 that counts number of times of substrate processing by each of the processing unit MPC. The scheduler 25 prepares a time chart representing an operation scheme for the plurality of units based on a production information in a manner such that all of the steps that is to be carried out by the plurality of units according to the processing details included in the processing informations, is completed by the end time limit. And the main controller 6, by controlling a plurality of ON/OFF switching devices according to time chart, makes a plurality of unit U operate by supplying electric power thereto — the figures show the number of sheets/products and start/end times].
But Hashimoto fails to clearly specify generating an input variable comprising processing speed of the plurality of process devices.
However, Quiros teaches generating an input variable comprising processing speed of the plurality of process devices [0013-0018 — The machine intelligence in the level 1 coordination systems 140 may make adjustments to any part of the manufacturing plan, e.g., based on resource availability, capacity, speed, reliability, or other characteristic of the devices and systems in the industrial environment 100, and also based on physical properties of the components and environments on which the worker systems execute their tasks. For instance, the level 1 coordination system 140 may reorder or replace tasks that are not achievable with substitute tasks that are currently achievable].
Hashimoto and Quiros are analogous art. They relate to industrial control systems.
Therefore at the time the invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above apparatus, as taught by Hashimoto, by incorporating the above limitations, as taught by Quiros.
One of ordinary skill in the art would have been motivated to do this modification in order to enable coordination between manufacturing devices, as suggested by Quiros [0013-0018].
Regarding claim 11, Hashimoto teaches method of manufacturing a display device [0001 — The present invention relates to a substrate processing apparatus for processing substrate and an electric power source management method of managing electric power supply therefor. Examples of substrates to be processed include semiconductor substrates, glass substrates for liquid crystal displays, glass substrates for plasma displays, substrates for FEDs (field emission displays; 0046, Fig. 4 — a substrate processing apparatus], the method comprising:
performing, by a processor, a process, the processor including a first process line including a plurality of first process devices configured to perform a first process and a second process line including a plurality of second process devices configured to perform a second process [0041-0044, Figs. 2 and 4 — processing block 5 comprises a plurality of (for example, eight) processing units MPC… FIG. 4, a chemical supply unit CC1 at one side supplies chemical liquids to four processing units MPC 1 to 4, and a chemical supply unit CC2 at another side supplies chemical liquids to four processing units MPC 5 to 8; 0068 — Chemical liquid processing, rinse processing, and dry processing are sequentially carried out in the processing units MPC 1 to 4. (1-4, 2-4, 3-4, 4-4)];
generating, by a management unit, an input variable including a target number of products to be processed during a predefined time duration in the first process line, a target number of products to be processed during the predefined time duration in the second process line, a number of the plurality of first process devices, a number of the plurality of second process devices [0050, Fig. 4 — main controller 6 comprises a CPU (central processing unit) 23, a memory device 24, and a scheduler 25, which functions through execution of programs stored in the memory device 24 by the CPU 23. The scheduler 25 includes a counter 26 that counts number of times of substrate processing by each of the processing unit MPC. The scheduler 25 prepares a time chart representing an operation scheme for the plurality of units based on a production information in a manner such that all of the steps that is to be carried out by the plurality of units according to the processing details included in the processing informations, is completed by the end time limit. And the main controller 6, by controlling a plurality of ON/OFF switching devices according to time chart, makes a plurality of unit U operate by supplying electric power thereto — the figures show the number of sheets/products and start/end times and the number of devices]; and
receiving, by a tool control (TC) unit, an output variable from the management unit to control the processor according to the output variable, wherein the output variable includes information about a power saving process device operating in a power saving mode from among the plurality of first process devices and the plurality of second process devices, a power saving start time of the power saving process device, and a power saving end time of the power saving process device [0047-0050, Figs. 4-9 — By being controlled by the main controller 6, the ON/OFF switching device 22 switches between ON state and OFF state. Each of the unit U is supplied with electric power when corresponding ON/OFF switching device 22 is ON state… main controller 6 comprises a CPU (central processing unit) 23, a memory device 24, and a scheduler 25, which functions through execution of programs stored in the memory device 24 by the CPU 23. The scheduler 25 includes a counter 26 that counts number of times of substrate processing by each of the processing unit MPC. The scheduler 25 prepares a time chart representing an operation scheme for the plurality of units based on a production information in a manner such that all of the steps that is to be carried out by the plurality of units according to the processing details included in the processing informations, is completed by the end time limit. And the main controller 6, by controlling a plurality of ON/OFF switching devices according to time chart, makes a plurality of unit U operate by supplying electric power thereto — the figures show the number of sheets/products and start/end times].
But Hashimoto fails to clearly specify generating an input variable comprising processing speed of the plurality of process devices.
However, Quiros teaches generating an input variable comprising processing speed of the plurality of process devices [0013-0018 — The machine intelligence in the level 1 coordination systems 140 may make adjustments to any part of the manufacturing plan, e.g., based on resource availability, capacity, speed, reliability, or other characteristic of the devices and systems in the industrial environment 100, and also based on physical properties of the components and environments on which the worker systems execute their tasks. For instance, the level 1 coordination system 140 may reorder or replace tasks that are not achievable with substitute tasks that are currently achievable].
Hashimoto and Quiros are analogous art. They relate to industrial control systems.
Therefore at the time the invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by Hashimoto, by incorporating the above limitations, as taught by Quiros.
One of ordinary skill in the art would have been motivated to do this modification in order to enable coordination between manufacturing devices, as suggested by Quiros [0013-0018].
Regarding claim 10, the combination of Hashimoto and Quiros all the limitations of the base claims as outlined above.
Further, Hashimoto teaches the plurality of second process devices are each configured to perform the second process on the product on which the first process has been performed, and the first process is different from the second process [0061 — In the processing unit MPC 1 to 8, a chemical liquid processing, rinse processing, and dry processing are sequentially carried out.; 0068-0069 — Chemical liquid processing, rinse processing, and dry processing are sequentially carried out in the processing units MPC 1 to 4. (1-4, 2-4, 3-4, 4-4)].
Regarding claim 20, the combination of Hashimoto and Quiros all the limitations of the base claims as outlined above.
Further, Hashimoto teaches performing, via the plurality of second process devices, the second process on the product on which the first process has been performed, wherein the first process is different from the second process [0061 — In the processing unit MPC 1 to 8, a chemical liquid processing, rinse processing, and dry processing are sequentially carried out.; 0068-0069 — Chemical liquid processing, rinse processing, and dry processing are sequentially carried out in the processing units MPC 1 to 4. (1-4, 2-4, 3-4, 4-4)].
Claim(s) 2 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hashimoto and Quiros in view of Tomine U.S. Patent Publication No. 20060175553 (hereinafter Tomine).
Regarding claim 2, the combination of Hashimoto and Quiros teaches all the limitations of the base claims as outlined above.
Further, Hashimoto teaches that each of the plurality of first process devices and the plurality of second process devices, a power saving in the power saving mode is adjusted and the output variable further includes a power saving of the power saving process device [0047-0050, Figs. 4-9 — By being controlled by the main controller 6, the ON/OFF switching device 22 switches between ON state and OFF state. Each of the unit U is supplied with electric power when corresponding ON/OFF switching device 22 is ON state… main controller 6 comprises a CPU (central processing unit) 23, a memory device 24, and a scheduler 25, which functions through execution of programs stored in the memory device 24 by the CPU 23. The scheduler 25 includes a counter 26 that counts number of times of substrate processing by each of the processing unit MPC. The scheduler 25 prepares a time chart representing an operation scheme for the plurality of units based on a production information in a manner such that all of the steps that is to be carried out by the plurality of units according to the processing details included in the processing informations, is completed by the end time limit. And the main controller 6, by controlling a plurality of ON/OFF switching devices according to time chart, makes a plurality of unit U operate by supplying electric power thereto — the figures show the number of sheets/products and start/end times].
But the combination of Hashimoto and Quiros fails to clearly specify a degree of power saving in the power saving mode is adjusted to a plurality of levels and the output further includes a degree of power saving of the power saving process device.
However, Tomine teaches a degree of power saving in the power saving mode is adjusted to a plurality of levels and the output further includes a degree of power saving of the power saving process device [0048-0051, Figs. 2-4 — Referring to FIG. 2, the standby mode of the dry etching device 100 are divided into the following four levels: standby-0, standby-1, standby-2 and standby-3. The standby-0 refers to a level at which product processing is ready. The standby-1 to standby-3 refer to a level at which product processing is not ready because part of the devices making up the dry etching device 100 is in a low-energy standby mode or stop mode… more devices are in the low-energy standby mode or stop mode during the standby-2 than the standby-1. Furthermore, more devices are in the low-energy standby mode or stop mode during the standby-3 than the standby-2. This way energy consumption in the standby mode is reduced step by step with the sequentially lowered energy levels; 0082 — the dry etching device 100 corresponds to the semiconductor manufacturing equipment, and the wafer corresponds to the product. Also, the standby-1 and the product processing mode correspond to the "level at which product processing is ready". The standby-1, standby-2 and standby-3 correspond to the "low-energy level at which product processing is not ready" and the "plurality of patterns having different electric power and other energy requirements and different lengths of required time from each other". The controller 60 corresponds to the retrieving part, the comparison part and the controlling part].
Hashimoto, Quiros and Tomine are analogous art. They relate to industrial control systems.
Therefore at the time the invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above apparatus, as taught by the combination of Hashimoto and Quiros, by incorporating the above limitations, as taught by Tomine.
One of ordinary skill in the art would have been motivated to do this modification in order to maintain low energy consumption and saving energy while dealing with changes to production plans and accounting for restart times, as suggested by Tomine [0086-0088].
Regarding claim 12, the combination of Hashimoto and Quiros teaches all the limitations of the base claims as outlined above.
Further, Hashimoto teaches that in each of the plurality of first process devices and the plurality of second process devices, adjusting a power saving in the power saving mode i, and including a power saving of the power saving process device in the output variable [0047-0050, Figs. 4-9 — By being controlled by the main controller 6, the ON/OFF switching device 22 switches between ON state and OFF state. Each of the unit U is supplied with electric power when corresponding ON/OFF switching device 22 is ON state… main controller 6 comprises a CPU (central processing unit) 23, a memory device 24, and a scheduler 25, which functions through execution of programs stored in the memory device 24 by the CPU 23. The scheduler 25 includes a counter 26 that counts number of times of substrate processing by each of the processing unit MPC. The scheduler 25 prepares a time chart representing an operation scheme for the plurality of units based on a production information in a manner such that all of the steps that is to be carried out by the plurality of units according to the processing details included in the processing informations, is completed by the end time limit. And the main controller 6, by controlling a plurality of ON/OFF switching devices according to time chart, makes a plurality of unit U operate by supplying electric power thereto — the figures show the number of sheets/products and start/end times].
But the combination of Hashimoto and Quiros fails to clearly specify adjusting a degree of power saving in the power saving mode i to a selected level of a plurality of level and including a degree of power saving of the power saving process device in the output variable.
However, Tomine teaches adjusting a degree of power saving in the power saving mode i to a selected level of a plurality of level and including a degree of power saving of the power saving process device in the output variable [0048-0051, Figs. 2-4 — Referring to FIG. 2, the standby mode of the dry etching device 100 are divided into the following four levels: standby-0, standby-1, standby-2 and standby-3. The standby-0 refers to a level at which product processing is ready. The standby-1 to standby-3 refer to a level at which product processing is not ready because part of the devices making up the dry etching device 100 is in a low-energy standby mode or stop mode… more devices are in the low-energy standby mode or stop mode during the standby-2 than the standby-1. Furthermore, more devices are in the low-energy standby mode or stop mode during the standby-3 than the standby-2. This way energy consumption in the standby mode is reduced step by step with the sequentially lowered energy levels; 0082 — the dry etching device 100 corresponds to the semiconductor manufacturing equipment, and the wafer corresponds to the product. Also, the standby-1 and the product processing mode correspond to the "level at which product processing is ready". The standby-1, standby-2 and standby-3 correspond to the "low-energy level at which product processing is not ready" and the "plurality of patterns having different electric power and other energy requirements and different lengths of required time from each other". The controller 60 corresponds to the retrieving part, the comparison part and the controlling part].
Hashimoto, Quiros and Tomine are analogous art. They relate to industrial control systems.
Therefore at the time the invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by the combination of Hashimoto and Quiros, by incorporating the above limitations, as taught by Tomine.
One of ordinary skill in the art would have been motivated to do this modification in order to maintain low energy consumption and saving energy while dealing with changes to production plans and accounting for restart times, as suggested by Tomine [0086-0088].
Claim(s) 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hashimoto and Quiros in view of Fujii et al. U.S. Patent Publication No. 20060102858 (hereinafter Fujii).
Regarding claim 5, the combination of Hashimoto and Quiros teaches all the limitations of the base claims as outlined above.
Further, Hashimoto teaches the management unit [050, Fig. 4 — main controller 6 comprises a CPU (central processing unit) 23, a memory device 24, and a scheduler 25, which functions through execution of programs stored in the memory device 24 by the CPU 23. The scheduler 25 includes a counter 26 that counts number of times of substrate processing by each of the processing unit MPC. The scheduler 25 prepares a time chart representing an operation scheme for the plurality of units based on a production information in a manner such that all of the steps that is to be carried out by the plurality of units according to the processing details included in the processing informations, is completed by the end time limit. And the main controller 6, by controlling a plurality of ON/OFF switching devices according to time chart, makes a plurality of unit U operate by supplying electric power thereto].
But the combination of Hashimoto and Quiros fails to clearly specify that a management unit is further configured to generate an inquiry signal about a current power saving state of the processor.
However, Fujii teaches that a management unit is further configured to generate an inquiry signal about a current power saving state of the processor [0603 — the processing-machine setting unit 117 confirms whether power is the ON state or the OFF state in each of the second processing machines 5a to 5h, thereby confirming the number of device in the operation state used for the production process of the second processing machine 5. Further, for example, the measuring-machine setting unit 116 confirms whether power is the ON state or the OFF state in each of the measuring machines; 0687 — the processing-machine setting unit 117 transmits the start signal to the data collecting unit 111].
Hashimoto, Quiros and Fujii are analogous art. They relate to industrial control systems.
Therefore at the time the invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above apparatus, as taught by the combination of Hashimoto and Quiros, by incorporating the above limitations, as taught by Fujii.
One of ordinary skill in the art would have been motivated to do this modification in order to confirm the operating/power state of each machine, as taught by Fujii [0603].
Regarding claim 15, the combination of Hashimoto and Quiros teaches all the limitations of the base claims as outlined above.
Further, Hashimoto teaches the management unit [050, Fig. 4 — main controller 6 comprises a CPU (central processing unit) 23, a memory device 24, and a scheduler 25, which functions through execution of programs stored in the memory device 24 by the CPU 23. The scheduler 25 includes a counter 26 that counts number of times of substrate processing by each of the processing unit MPC. The scheduler 25 prepares a time chart representing an operation scheme for the plurality of units based on a production information in a manner such that all of the steps that is to be carried out by the plurality of units according to the processing details included in the processing informations, is completed by the end time limit. And the main controller 6, by controlling a plurality of ON/OFF switching devices according to time chart, makes a plurality of unit U operate by supplying electric power thereto].
But the combination of Hashimoto and Quiros fails to clearly specify generating, by the management unit, an inquiry signal about a current power saving state of the processor.
However, Fujii teaches generating, by the management unit, an inquiry signal about a current power saving state of the processor [0603 — the processing-machine setting unit 117 confirms whether power is the ON state or the OFF state in each of the second processing machines 5a to 5h, thereby confirming the number of device in the operation state used for the production process of the second processing machine 5. Further, for example, the measuring-machine setting unit 116 confirms whether power is the ON state or the OFF state in each of the measuring machines; 0687 — the processing-machine setting unit 117 transmits the start signal to the data collecting unit 111].
Hashimoto, Quiros and Fujii are analogous art. They relate to industrial control systems.
Therefore at the time the invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by the combination of Hashimoto and Quiros, by incorporating the above limitations, as taught by Fujii.
One of ordinary skill in the art would have been motivated to do this modification in order to confirm the operating/power state of each machine, as taught by Fujii [0603].
Claim(s) 9 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over the combination of Hashimoto, Quiros and Fujii in view of Maturana et al. U.S. Patent Publication No. 20050034023 (hereinafter Maturana).
Regarding claim 9, the combination of Hashimoto, Quiros and Fujii teaches all the limitations of the base claims as outlined above.
Further, Hashimoto teaches the management unit [050, Fig. 4 — main controller 6 comprises a CPU (central processing unit) 23, a memory device 24, and a scheduler 25, which functions through execution of programs stored in the memory device 24 by the CPU 23. The scheduler 25 includes a counter 26 that counts number of times of substrate processing by each of the processing unit MPC. The scheduler 25 prepares a time chart representing an operation scheme for the plurality of units based on a production information in a manner such that all of the steps that is to be carried out by the plurality of units according to the processing details included in the processing informations, is completed by the end time limit. And the main controller 6, by controlling a plurality of ON/OFF switching devices according to time chart, makes a plurality of unit U operate by supplying electric power thereto].
Further, Fujii teaches the management unit is further configured to generate the inquiry signal [0603 — the processing-machine setting unit 117 confirms whether power is the ON state or the OFF state in each of the second processing machines 5a to 5h, thereby confirming the number of device in the operation state used for the production process of the second processing machine 5. Further, for example, the measuring-machine setting unit 116 confirms whether power is the ON state or the OFF state in each of the measuring machines; 0687 — the processing-machine setting unit 117 transmits the start signal to the data collecting unit 111].
But the combination of Hashimoto and Quiros fails to clearly specify that the management unit is further configured to generate the signal multiple times at regular time intervals.
However, Maturana teaches that the management unit is further configured to generate the signal multiple times at regular time intervals [0065, Fig. 5 — the LDF(s) 66 regularly communicate with the GDF(s) 64 and provide information thereto, by way of a periodic, "heart-beating" signal or "sanity" check. By providing such regular communications between the LDF(s) 66 and the GDF(s), the robustness of the system is increased.; 0057 — global directory facilitators (GDFs) 64 and one or more local directory facilitators (LDFs) 66].
Hashimoto, Quiros, Fujii and Maturana are analogous art. They relate to industrial control systems.
Therefore at the time the invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above apparatus, as taught by the combination of Hashimoto and Quiros, by incorporating the above limitations, as taught by Fujii.
One of ordinary skill in the art would have been motivated to do this modification in order to increase the robustness of the system, as taught by Maturana [0065].
Regarding claim 19, the combination of Hashimoto, Quiros and Fujii teaches all the limitations of the base claims as outlined above.
Further, Fujii teaches generating the inquiry signal [0603 — the processing-machine setting unit 117 confirms whether power is the ON state or the OFF state in each of the second processing machines 5a to 5h, thereby confirming the number of device in the operation state used for the production process of the second processing machine 5. Further, for example, the measuring-machine setting unit 116 confirms whether power is the ON state or the OFF state in each of the measuring machines; 0687 — the processing-machine setting unit 117 transmits the start signal to the data collecting unit 111].
But the combination of Hashimoto and Quiros fails to clearly specify that generating the signal multiple times at regular time intervals.
However, Maturana teaches generating the signal multiple times at regular time intervals [0065, Fig. 5 — the LDF(s) 66 regularly communicate with the GDF(s) 64 and provide information thereto, by way of a periodic, "heart-beating" signal or "sanity" check. By providing such regular communications between the LDF(s) 66 and the GDF(s), the robustness of the system is increased.; 0057 — global directory facilitators (GDFs) 64 and one or more local directory facilitators (LDFs) 66].
Hashimoto, Quiros, Fujii and Maturana are analogous art. They relate to industrial control systems.
Therefore at the time the invention was made, it would have been obvious to a person of ordinary skill in the art to modify the above method, as taught by the combination of Hashimoto and Quiros, by incorporating the above limitations, as taught by Fujii.
One of ordinary skill in the art would have been motivated to do this modification in order to increase the robustness of the system, as taught by Maturana [0065].
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Matyuskin et al. U.S. Patent Publication No. 20080017104 discloses an annealing system for semiconductor manufacturing
Kou et al. U.S. Patent Publication No. 20220369430 that discloses a laser annealing system for semiconductor manufacturing.
Note that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
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/BERNARD G LINDSAY/
Primary Examiner, Art Unit 2119
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