Prosecution Insights
Last updated: October 23, 2026
Application No. 18/583,892

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
Feb 22, 2024
Priority
Mar 01, 2023 — JP 2023-031379
Examiner
MAI, ANH D
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
KIOXIA Corporation
OA Round
1 (Non-Final)
38%
Grant Probability
At Risk
1-2
OA Rounds
1y 0m
Est. Remaining
47%
With Interview

Examiner Intelligence

Grants only 38% of cases
38%
Career Allowance Rate
267 granted / 709 resolved
-30.3% vs TC avg
Moderate +10% lift
Without
With
+9.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
38 currently pending
Career history
769
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
44.6%
+4.6% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
30.2%
-9.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 709 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Claims Applicant’s election without traverse of Group II and Species 1, as shown in FIG. 8, in the reply filed on July 26, 2026 is acknowledged. Applicant identifies claims 11-20 are readable on the Invention II and Species 1. Non-Elected Invention, Group I, claims 1-10 have been withdrawn from consideration. Claims 1-120 are pending. Claim 18 recites: “The semiconductor device of claim 11, wherein the member has a porous structure”. This limitation directs to non-elected Species as shown in FIG. 17. Therefore, claim 18 is effectively withdrawn from consideration. With abundance of caution, an action on merit of claim 18 is included. However, Applicant must withdraw claim 18, since the limitation of claim 18 being directed to non-elected Species. Action on merits of Elected Invention and/or Species, claims 11-20 follows. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) submitted on February 22, 2024; September 23, 2024; December 26, 2024 and August 20, 2-26 have been considered by the examiner. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: AN INTEMEDIATE STRUCTURE OF A SEMICONDUCTOR DEVICE HAVING A THERMAL DIFFUSION LAYER FORMED INSIDE A LASER PEELING LAYER PROVIDED ABOVE A SECOND CIRCUIT Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 1-17 and 19-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 11, lines 13-18, recites: “a thermal diffusion layer provided inside the laser peeling film, the thermal diffusion layer including a member distributed in a plane parallel to a front surface of the semiconductor substrate, and the member having a coefficient of thermal conductivity higher than that of the laser peeling film”. Since the “thermal diffusion layer” (130/140) is a part of the laser diffusion film (100), the “thermal diffusion layer” (including a member) cannot has a coefficient of thermal conductivity higher than itself. Therefore, claim 11 and all dependent claims thereof, are indefinite. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 11-19 are rejected under 35 U.S.C. 103 as being unpatentable over MATSUO et al. (US. Pub. No. 2021/0074672) in view of KIZU et al. (US. Pub. No. 2023/0395395) of record. With respect to claim 1, As best understood by the Examiner, MATSUO teaches a semiconductor device substantially as claimed including: a semiconductor substrate (40); a first circuit layer (50) provided on the semiconductor substrate (40) and including a first semiconductor circuit; a bonding layer (16/35) provided on the first circuit layer and including a plurality of pads (28/37) coupled to the first semiconductor circuit (50); a second circuit layer (11) provided on the bonding layer and including a second semiconductor circuit coupled to the pads; a peeling film (30) provided above the second circuit layer (11). (See FIGs. 2B, 6). Thus, MATSUO is shown to teach all the features of the claim with the exception of explicitly disclosing the peeling layer being a laser peeling layer. However, KIZU teaches a semiconductor device having a separation layer including: a laser peeling film provided above the second circuit layer (101); a thermal diffusion layer (108) provided inside the laser peeling film, the thermal diffusion layer (108) including a member (108) distributed in a plane parallel to a front surface of semiconductor substrate (104), and the member (108, metal) having a coefficient of thermal conductivity higher than that of the laser peeling film (resin). (See FIG. 7C). Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of MATSUO having the separation layer utilizing the laser peeling layer as taught by KIZU for the same intended purpose of separation without damaging the circuit that formed on the semiconductor substrate. With respect to claim 12, in view of KIZU, the thermal diffusion layer (108) is arranged to overlap the first semiconductor circuit in a direction vertical to the semiconductor substrate. With respect to claim 13, in view of KIZU, the thermal diffusion layer includes a plurality of first members (101, 210), each extending in a first direction parallel to the front surface of the semiconductor substrate (211) and having a coefficient of thermal conductivity higher than that of the laser peeling film (202), and the first members are arranged at substantially regular intervals in a second direction parallel to the front surface of the semiconductor substrate and intersecting the first direction. (See FIGs. 4, 7C, 26, 48D). With respect to claim 14, in view of KIZU, a distance in the second direction between adjacent two of the first members (101, 212, …) is smaller than a wavelength (700 nm to 200 nm) of a laser beam transmitted through the semiconductor substrate and absorbed by the laser peeling film. Although KIZU does not disclose the distance between adjacent two of the first members, however, the semiconductor device of KIZU is effectively separated utilizing laser beam having wavelength of 700 nm to 200 nm. It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."). Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of MATSUO, in view of KIZU, having the distance in the second direction between adjacent two of the first members being smaller than the wavelength (700 nm to 200 nm) of a laser beam to facilitate separation without damaging to the substrate through a routine optimization. With respect to claim 15, in view of KIZU, the thermal diffusion layer includes a plurality of second members (111), each extending in the second direction, arranged at a height different from the first members (108), and having a coefficient of thermal conductivity higher than that of the laser peeling film, the second members (111) being arranged at substantially regular intervals in the first direction. (See FIG. 5K). With respect to claim 16, in view of KIZU, each of the distance in the second direction between adjacent two of the first members and the distance in the first direction between adjacent two of the second members is smaller than a wavelength of a laser beam transmitted through the semiconductor substrate and absorbed by the laser peeling film. Similar to claim 14 above, Although KIZU does not disclose the distance between adjacent two of the first members or the second members, however, the semiconductor device of KIZU is effectively separated utilizing laser beam having wavelength of 700 nm to 200 nm. It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages."). Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of MATSUO, in view of KIZU, having the distance in the second direction between adjacent two of the first members and the second members being smaller than the wavelength (700 nm to 200 nm) of a laser beam to facilitate separation without damaging to the substrate through a routine optimization. With respect to claim 17, in view of KIZU, the member is made of metal. With respect to claim 18, As best understood by the Examiner, the (separation layer) member of MATSUO has a porous structure. With respect to claim 19, the second semiconductor circuit (11) of MATSUO includes a plurality of memory cells capable of storing data in a nonvolatile manner, and the first semiconductor circuit (50) includes a CMOS circuit configured to control the memory cells. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over MATSUO ‘672 and KIZU ‘395 as applied to claim 11 above, and further in view of ISOGAI et al. (US. Pub. No. 2022/0013539). MATSUO, in view of KIZU, teaches the semiconductor device as described in claim 11 including: including plurality of pads (28/37) coupled to the first semiconductor circuit (50). Thus, MATSUO and KIZU are shown to teach all the features of the claim with the exception of explicitly disclosing each of the pads having a reverse tapered portion. However, ISOGAI teaches a semiconductor device including: a bonding layer provided on first circuit layer and including a plurality of pads (17/22) coupled to the first semiconductor circuit, wherein each of the pads has a reverse tapered portion on a side of the first circuit layer and a tapered portion on a side of the second circuit layer. (See FIG. 1). Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form each of the pad of MATSUO having a reverse tapered portion on a side of the first circuit layer and a tapered portion on a side of the second circuit layer as taught by ISOGAI for the same intended purpose of providing contact between the first and second circuit. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 10:00-4:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue A Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANH D MAI/Primary Examiner, Art Unit 2893
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Prosecution Timeline

Feb 22, 2024
Application Filed
Oct 06, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
38%
Grant Probability
47%
With Interview (+9.6%)
3y 8m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 709 resolved cases by this examiner. Grant probability derived from career allowance rate.

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