DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,8,9,11,12 is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Yoshimizu et al., (Yoshimizu) US 2022/0068961.
Regarding claim 1, Yoshimizu shows in FIG. 1-39, a semiconductor memory device comprising: a stacked body (stacked body in chip Cm and Chip Cp)[0033,0034] including a plurality of gate electrode layers (110)[0038] and a plurality of insulating layers (101)[0051], wherein the plurality of gate electrode layers (110) and the plurality of insulating layers (101) are alternately stacked one layer at a time in a first direction; a plurality of columnar bodies (120)[0052] extending in the first direction in the stacked body; a plurality of bit lines (BL layers connected to each 120)(see FIG. 5) disposed on one side in the first direction with respect to the stacked body, located in a second direction intersecting the first direction, and extending in a third direction intersecting with the first direction and the second direction (see FIG. 5); a plurality of contacts (above each BL) (see FIG. 5) located between the plurality of columnar bodies (120) and the plurality of bit lines (BL); a plurality of dividing portions (150)[0050] located separately in the third direction, each dividing portion (150) extending in the first direction in the stacked body, and dividing one or more gate electrode layers (110) including the lowermost layer of the plurality of gate electrode layers (110) in the third direction, when the one side is the lower side, wherein the plurality of columnar bodies (150) includes five columnar bodies (see FIG. 5)( the bodies can be duplicated) which are located alternately in two rows adjacent in the second direction and each of the two rows extending in the third direction in a region between two adjacent dividing portions of the plurality of dividing portions (see FIG. 5), and regarding each columnar body provided in the five columnar bodies (150), a separate bit line (separate bit line formed under each 120) (see FIG. 5) provided in the plurality of bit lines is present between a bit line disposed in the plurality of bit lines and electrically connected to the columnar body (120), and each bit line (BL) disposed in the plurality of bit lines and electrically connected to a columnar body (120) adjacent to that columnar body (120) at the shortest interval among the five columnar bodies (see FIG. 5).
As for the columnar bodies, they could be duplicated and connected to the pluralities of bit line (BL metal and perpendicular extension connected to the bodies), since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. 2144.04
Regarding claim 8, Yoshimizu shows in FIG. 1-39, a semiconductor memory device comprising: a stacked body (Cp, Cm stacked) [0033,0034] including a plurality of gate electrode layers (110) and a plurality of insulating layers (101), wherein the plurality of gate electrode layers (110) and the plurality of insulating layers (101) are alternately stacked one layer at a time in a first direction; a plurality of columnar bodies (120) extending in the first direction in the stacked body; a plurality of bit lines (BL and multiple BLs extensions, see FIG. 5) disposed on one side in the first direction with respect to the stacked body (Cp, Cm stacked), located in a second direction intersecting with the first direction, and extending in a third direction intersecting with the first direction and the second direction (see FIG. 5); a plurality of contacts (above bit lines BL) (see FIG. 5) located between the plurality of columnar bodies (120) and the plurality of bit lines (BL); a plurality of dividing portions (150) located separately in the third direction, each dividing portion (150) extending in the first direction in the stacked body (see FIG. 5), and dividing one or more gate electrode layers (110) including the lowermost layer of the plurality of gate electrode layers in the third direction, when the one side is the lower side, wherein the plurality of columnar bodies (120) include a first columnar body, a second columnar body, a third columnar body, a fourth columnar body, and a fifth columnar body, and the first columnar body, the second columnar body, the third columnar body, the fourth columnar body, and the fifth columnar body (multiple 120s)(see FIG. 5) are disposed in a region between two adjacent dividing portions among the plurality of dividing portions, and located in this order in the third direction so as to at least partially overlap each other when viewed from the third direction, the plurality of bit lines (BL) includes a first bit line (see FIG. 5), a second bit line, a third bit line, a fourth bit line, and a fifth bit line, and the first bit line, the second bit line, the third bit line, the fourth bit line, and the fifth bit line (see FIG. 5) are located in this order in the second direction, the first columnar body (120) overlaps the first bit line (BL) (see FIG. 5) when viewed from the first direction and is electrically connected to the first bit line, the second columnar body (other 120) overlaps the fourth bit line (see FIG. 5) when viewed from the first direction and is electrically connected to the fourth bit line, the third columnar body (120) overlaps the second bit line when viewed from the first direction and is electrically connected to the second bit line, the fourth columnar body (120) overlaps the fifth bit line when viewed from the first direction and is electrically connected to the fifth bit line, and the fifth columnar body (120) overlaps the third bit line when viewed from the first direction and is electrically connected to the third bit line (see FIG. 5)(multiple 120s are shown).
As for the columnar bodies, they could be duplicated and connected to the pluralities of bit line (BL metal and perpendicular extension connected to the bodies), since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. 2144.04
Regarding claim 9, Yoshimizu shows in FIG. 1-39, a semiconductor memory device comprising: a stacked body (Cp, Cm stacked) including a plurality of gate electrode layers (110) and a plurality of insulating layers (101), wherein the plurality of gate electrode layers (110) and the plurality of insulating layers (101) are alternately stacked one layer at a time in a first direction; a plurality of columnar bodies (120) extending in the first direction in the stacked body; a plurality of bit lines (BL) disposed on one side in the first direction with respect to the stacked body, located in a second direction intersecting with the first direction, and extending in a third direction intersecting with the first direction and the second direction; a plurality of contacts (abve BLs) located between the plurality of columnar bodies (120) and the plurality of bit lines (BL); a plurality of dividing portions located separately in the third direction, each dividing portion extending in the first direction in the stacked body (Cp, Cm stacked), and dividing one or more gate electrode layers (110) including the lowermost layer of the plurality of gate electrode layers (110) in the third direction, when the one side is the lower side, wherein the plurality of columnar bodies (120) include a first columnar body, a second columnar body, a third columnar body, a fourth columnar body, and a fifth columnar body, and the first columnar body, the second columnar body, the third columnar body, the fourth columnar body, and the fifth columnar body (120) are disposed in a region between two adjacent dividing portions among the plurality of dividing portions, and located in this order in the third direction so as to at least partially overlap each other when viewed from the third direction, the plurality of bit lines (BL) includes a first bit line, a second bit line, a third bit line, a fourth bit line, and a fifth bit line, and the first bit line, the second bit line, the third bit line, the fourth bit line, and the fifth bit line (Multiple BLs) are located in this order in the second direction, the first columnar body overlaps the third bit line when viewed from the first direction and is electrically connected to the third bit line, the second columnar body (120) overlaps the fifth bit line (BL) when viewed from the first direction and is electrically connected to the fifth bit line, the third columnar body (120) overlaps the second bit line when viewed from the first direction and is electrically connected to the second bit line, the fourth columnar body (120) overlaps the fourth bit line when viewed from the first direction and is electrically connected to the fourth bit line, and the fifth columnar body (120) overlaps the first bit line when viewed from the first direction and is electrically connected to the first bit line (BL).
As for the columnar bodies, they could be duplicated and connected to the pluralities of bit line (BL metal and perpendicular extension connected to the bodies), since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. 2144.04
Regarding claim 11, Yoshimizu shows in FIG. 1-39, a semiconductor memory device, wherein the gate electrode layers (110) include at least one of tungsten or molybdenum [0039].
Regarding claim 12, Yoshimizu shows in FIG. 1-39, a semiconductor memory device, wherein the insulating layers include silicon and oxygen [0039].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimizu.
Regarding claim 2, Yoshimizu shows in FIG. 1-39, a semiconductor memory device, wherein a plurality of regions defined by the plurality of dividing portions (150) includes a first region and a second region adjacent to each other, the plurality of columnar bodies (120) includes a first columnar body, a second columnar body, a third columnar body, a fourth columnar body, a fifth columnar body, a sixth columnar body, a seventh columnar body, an eighth columnar body, a ninth columnar body, and a tenth columnar body, the first columnar body, the second columnar body, the third columnar body, the fourth columnar body, and the fifth columnar body are disposed in the first region, located alternately in the two rows, and located in this order with respect to the third direction, the sixth columnar body, the seventh columnar body, the eighth columnar body (120) are disposed in the second region, located alternately in the two rows, and located in this order with respect to the third direction, the plurality of bit lines (BL)(see FIG. 5) includes a first bit line, a second bit line, a third bit line, a fourth bit line, and a fifth bit line, and the first bit line, the second bit line, the third bit line, the fourth bit line, and the fifth bit line (BL)(see FIG. 5) are located in this order in the second direction, the first columnar body (120) overlaps the first bit line when viewed from the first direction and is electrically connected to the first bit line (BL)(see FIG. 5), the second columnar body (120) overlaps the fourth bit line (BL)(see FIG. 5) when viewed from the first direction and is electrically connected to the fourth bit line, the third columnar body (120) overlaps the second bit line when viewed from the first direction and is electrically connected to the second bit line (BL)(see FIG. 5), the fourth columnar body (120) overlaps the fifth bit line when viewed from the first direction and is electrically connected to the fifth bit line, the fifth columnar body (120) overlaps the third bit line when viewed from the first direction and is electrically connected to the third bit line, the sixth columnar body (120) overlaps the fifth bit line when viewed from the first direction and is electrically connected to the fifth bit line, the seventh columnar body (120) overlaps the second bit line when viewed from the first direction and is electrically connected to the second bit line, the eighth columnar body (120) overlaps the fourth bit line when viewed from the first direction and is electrically connected to the fourth bit line.
Yoshimizu discloses the claimed invention except for a device having a ninth columnar body, and a tenth columnar body, the ninth columnar body overlaps the first bit line when viewed from the first direction and is electrically connected to the first bit line, and the tenth columnar body overlaps the third bit line when viewed from the first direction and is electrically connected to the third bit line. It would have been obvious to one of ordinary skill in the art at the time of the invention was made to have a device having a ninth columnar body, and a tenth columnar body, the ninth columnar body overlaps the first bit line when viewed from the first direction and is electrically connected to the first bit line, and the tenth columnar body overlaps the third bit line when viewed from the first direction and is electrically connected to the third bit line because FIG. 3 shows multiple column 120 that would be connected to respective BL, FIG. 5 shows the BLs connected to at least 8 columnar body, thus, the multiple column 120 can be connected to multiple BLs, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 3, Yoshimizu shows in FIG. 1-39, a semiconductor memory device, wherein the plurality of regions includes a third region located on the opposite side of the first region with respect to the second region and adjacent to the second region (see FIG. 3,5), the plurality of columnar bodies (120) includes an eleventh columnar body (120), a twelfth columnar body, a thirteenth columnar body, a fourteenth columnar body, and a fifteenth columnar body, the eleventh columnar body, the twelfth columnar body, the thirteenth columnar body, the fourteenth columnar body, and the fifteenth columnar body (120) (see FIG. 3,5) are disposed in the third region, located alternately in the two rows, and located in this order with respect to the third direction, the eleventh columnar body (120) overlaps the first bit line when viewed from the first direction and is electrically connected to the first bit line, the twelfth columnar body (120) overlaps the fourth bit line when viewed from the first direction and is electrically connected to the fourth bit line, the thirteenth columnar body (120)overlaps the second bit line when viewed from the first direction and is electrically connected to the second bit line, the fourteenth columnar body (120) overlaps the fifth bit line (BL) when viewed from the first direction and is electrically connected to the fifth bit line, and the fifteenth columnar body (120) overlaps the third bit line when viewed from the first direction and is electrically connected to the third bit line (BL).
FIG. 3 shows multiple column 120 that would be connected to respective BL, FIG. 5 shows the BLs connected to at least 8 columnar body, thus, the multiple column 120 can be connected to multiple BLs, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 4, Yoshimizu shows in FIG. 1-39, a semiconductor memory device wherein the plurality of regions divided by the plurality of dividing portions (150) includes a first region and a second region adjacent to each other, the plurality of columnar bodies (120) includes a first columnar body, a second columnar body, a third columnar body, a fourth columnar body, a fifth columnar body, a sixth columnar body, a seventh columnar body, an eighth columnar body, a ninth columnar body, and a tenth columnar body (120), the first columnar body, the second columnar body, the third columnar body, the fourth columnar body, and the fifth columnar body (120) are disposed in the first region, located alternately in the two rows, and located in this order with respect to the third direction (see FIG. 3,5), the sixth columnar body, the seventh columnar body, the eighth columnar body, the ninth columnar body, and the tenth columnar body are disposed in the second region and located alternately in the two rows (see FIG. 3,5), and located in this order with respect to the third direction, the plurality of bit lines includes a first bit line, a second bit line, a third bit line, a fourth bit line, and a fifth bit line (multiple BLs), and the first bit line, the second bit line, the third bit line, the fourth bit line, and the fifth bit line (BL)are located in this order in the second direction, the first columnar body overlaps the third bit line when viewed from the first direction and is electrically connected to the third bit line (see FIG. 3,5), the second columnar body (120) overlaps the fifth bit line when viewed from the first direction and is electrically connected to the fifth bit line, the third columnar body (120) overlaps the second bit line when viewed from the first direction and is electrically connected to the second bit line (see FIG. 3,5), the fourth columnar body (120)overlaps the fourth bit line when viewed from the first direction and is electrically connected to the fourth bit line, the fifth columnar body (120) overlaps the first bit line when viewed from the first direction and is electrically connected to the first bit line (see FIG. 3,5), the sixth columnar body (120) overlaps the third bit line when viewed from the first direction and is electrically connected to the third bit line, the seventh columnar body overlaps the first bit line when viewed from the first direction and is electrically connected to the first bit line (see FIG. 3,5), the eighth columnar body (120) overlaps the fourth bit line when viewed from the first direction and is electrically connected to the fourth bit line, the ninth columnar body overlaps the second bit line when viewed from the first direction and is electrically connected to the second bit line, and the tenth columnar body (120)overlaps the fifth bit line when viewed from the first direction and is electrically connected to the fifth bit line (see FIG. 3,5).
FIG. 3 shows multiple column 120 that would be connected to respective BL, FIG. 5 shows the BLs connected to at least 8 columnar body, thus, the multiple column 120 can be connected to multiple BLs, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 5, Yoshimizu shows in FIG. 1-39, a semiconductor memory device, wherein the plurality of regions includes a third region located on the opposite side of the first region with respect to the second region and adjacent to the second region, the plurality of columnar bodies (120) includes an eleventh columnar body (120), a twelfth columnar body, a thirteenth columnar body, a fourteenth columnar body, and a fifteenth columnar body, the eleventh columnar body, the twelfth columnar body, the thirteenth columnar body (see FIG. 3,5), the fourteenth columnar body, and the fifteenth columnar body (120) are provided in the third region, located alternately in the two rows (see FIG. 3,5), and located in this order with respect to the third direction, the eleventh columnar body (120) overlaps the third bit line (BL) (see FIG. 3,5)when viewed from the first direction and is electrically connected to the third bit line, the twelfth columnar body overlaps the fifth bit line (BL) when viewed from the first direction and is electrically connected to the fifth bit line, the thirteenth columnar body overlaps the second bit line when viewed from the first direction and is electrically connected to the second bit line, the fourteenth columnar body (120) overlaps the fourth bit line (BL) (see FIG. 3,5) when viewed from the first direction and is electrically connected to the fourth bit line, and the fifteenth columnar body (120) overlaps the first bit line when viewed from the first direction and is electrically connected to the first bit line (BL). FIG. 3 shows multiple column 120 that would be connected to respective BL, FIG. 5 shows the BLs connected to at least 8 columnar body, thus, the multiple column 120 can be connected to multiple BLs, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 6, Yoshimizu shows in FIG. 1-39, a semiconductor memory device, wherein the fifth columnar body (120) and the sixth columnar body (120) are located separately on both sides of one dividing portion disposed in the plurality of dividing portions, and when viewed from the first direction, a center-to-center distance between the fifth columnar body (120) and the sixth columnar body (120) (see FIG. 3,5) is the same as a center-to-center distance between the fourth columnar body and the fifth columnar body (120).
Regarding claim 7, Yoshimizu shows in FIG. 1-39, a semiconductor memory device, wherein when viewed from the first direction, the dividing portion overlaps with a part of the fifth columnar body (120) and overlaps with a part of the sixth columnar body (120).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimizu as applied to claims 1,8,9,11,12, and further in view of Kim et al., (Kim) US 2024/0023336.
Regarding claim 10, Yoshimizu differs from the claimed invention because he does not explicitly disclose a device wherein the semiconductor memory device includes a NAND flash memory.
Kim discloses [0046] a device wherein the semiconductor memory device includes a NAND flash memory.
Kim is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Yoshimizu. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching Kim in the device of Yoshimizu because it is a type of memory commonly known in the technology and provide a device with increased performance [0004]
Response to Arguments
Applicant's arguments filed 7/9/26 have been fully considered but they are not persuasive. Applicant argues that: “even though FIG. 5 appears to disclose bit lines (as asserted by the Office), no teaching or suggestion of the arrangement of bit lines in Yoshimizu is found.” The Examiner respectfully disagrees because Yoshimizu shows in FIG. 5, and discloses columnar bodies connected to the pluralities of bit line (BL metal and perpendicular extension connected to the bodies).
As for the columnar bodies, they could be duplicated and connected to the pluralities of bit line (BL metal and perpendicular extension connected to the bodies), since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. 2144.04
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/Primary Examiner, Art Unit 2813
Prosecution Insights