DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement filed on April 29, 2025 have all been considered and made of record (note the attached copy(ies) of form PTO-1449).
Drawings
Ten sheets of drawings were filed on February 22, 2024 and have been accepted by the examiner.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Election/Restrictions
Claims 11-16 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on May 18, 2026. Claims 1-10, and 17-26 are under consideration.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 9-10, 17, 19, 20, 22 and 23 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Bian et al. (US 10,429,582 B1, herein “Bian”) in view of Song et al. (US 2021/0302650 A1, herein “Song”) and further in view of Oxland et al. (US 2017/0125518 A1, herein “Oxland”).
Claim 1. Bian discloses a waveguide fabrication method comprising:
forming a stack of layers (SOI substrate includes silicon layer and buried oxide layer 16) wherein waveguides (10, 12, 14) are arranged on a buried oxide (BOX) layer 16 of the SOI substrate, the BOX layer 15 operates as a lower cladding providing confinement for the lower waveguides (10, 12, 14) (Col. 2, line 66 to col. 3, line 11). The lower waveguide (10, 12, 14) is composed of a silicon patterned from the single crystal semiconductor material of the device layer of SOI substrate. The lower waveguide (10, 12, 14) are surrounded by shallow trench isolation regions 20 that may be formed by patterning the device layer of the SOI substrate form trenches with lithography and etching, filling the trenches with silicon dioxide and planarizing with chemical mechanical polishing (CMP) (Col. 3, lines 35-56).
Bian does not explicitly teach the etch stop layer, patterning the etch stop layer and etching the waveguide layer after the patterning to form a waveguide and a chemical-mechanical polishing (CMP) control structure.
Song teaches forming a stack of layers (Fig. 21 shows SOI 106, oxide layer 108, etch stop layer 1926, and polish stop layer 1022 ),
patterning the etch stop layer (1926, Para [0040]) and etching the waveguide layer with the patterning (Para [0053]-[0057]) to form a waveguide (102A) and a chemical polishing (CMP) control structure (polish stop layer 1022);
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filling a space between the waveguide and the CMP control structure and performing CMP to reduce a thickness of the waveguide, wherein the CMP control structure controls the CMP of the waveguide (1022 functions as a polish stop in the CMP process) to prevent over polishing to an undesired thickness (Para [0053]-[0054]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the step of depositing etch stop layer (1926) to an SOI structure for forming waveguide (102A) would have been modifiable to the manufacturing steps of Bian since Bian teaches forming the trenches with lithography and etching; which implies an etch stop layer. Moreover, depositing the CMP control structure (1022) would have been obvious to one having ordinary skill before the effective filing date of the claimed invention since the CMP control structure is merely a layer of silicon nitride and would have been obvious to adapt in the CMP process of Bian. One motivation for depositing an etch stop layer is to form the waveguide having the CMP control structure as taught by Song so that the planarizing step of CMP would not over polish the waveguide layer.
However, Bian in view of Song do not teach the CMP control structure controls the CMP of the waveguide to form a transitional portion of the waveguide having a gradually changing thickness.
Oxland teaches a CMP process wherein polish stop pillar (502, 508) have different heights to control the gradually changing thickness of the planarized surface. Oxland also teaches filling removing dummy layer 112 and replacing the gate layer 112 with a dielectric.
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It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the varying height polishing stop pillar (502, 508) would be modifiable to the polish stop (1022) of Song for forming tapering waveguides which may require tapering in the height direction. One motivation for modifying single height polish stop with varying height polish stop is to control the height contour of the surface.
Claim 3. Bian / Song / Oxland teach the invention of claim 1 and Bian further teaches the
the waveguide has a width that gradually increases over the transitional portion of the waveguide. Fig. 1 shows waveguide (12) gradually widens to the width of waveguide (10).
Claim 4. Bian / Song / Oxland teach the invention of claim 1 and Bian further teaches waveguide layer comprises silicon (surface of SOI) and the cladding material comprises silicon dioxide (BOX) (Col. 2, line 66 to col. 3, line 11).
Claim 5. Bian / Song / Oxland teach the invention of claim 1 and Song further teaches the etch stop layer (1926) comprises silicon nitride (Song: Para [0059]).
Claim 6. Bian / Song / Oxland teach the invention of claim 4 and Bian / Song / Oxland further teaches the space between the waveguide and the CMP control structure is filled with the cladding material using a shallow trench isolation (STI) process (Bian: Col. 3, lines 37-56).
Claims 7 and 9. Bian / Song / Oxland teach the invention of claim 1, Bian / Song / Oxland further teaches in Fig. 5, wherein the CMP control structure (502, 508) controls the CMP of the waveguide to produce the transitional portion of the waveguide having the changing thickness which is monotonically increasing from a first portion of the waveguide to a second portion of the waveguide, wherein after performing the CMP a thickness of the first portion of the waveguide is smaller than a thickness of the second portion of the waveguide (Fig. 5 shows the different height polish stop pillars (502, 508) allows the contour of the substrate to monotonically increasing from a first portion (at 508) of the waveguide to a second portion (at the polish stop pillar unlabeled) of the waveguide. The transitional portion of the waveguide in Oxland’s invention does not include an abrupt thickness step (Fig. 5).
Claim 10. Bian / Song / Oxland teach the invention of claim 1, wherein Bian further teaches the forming of the stack of layers includes the waveguide layer of the stack of layers comprises a silicon layer of the SOI wafer and the cladding layer of the stack of layers comprises a buried oxide layer of the SOI wafer (Col. 3, lines 37-56). Bian further teaches the trenches 20 are formed through lithography or etching, which implies an etch stop layer to form the trenches 20.
Regarding claim 17, Bian discloses a waveguide fabrication method comprising:
forming a stack of layers (SOI substrate includes silicon layer and buried oxide layer 16) wherein waveguides (10, 12, 14) are arranged on a buried oxide (BOX) layer 16 of the SOI substrate, the BOX layer 15 operates as a lower cladding providing confinement for the lower waveguides (10, 12, 14) (Col. 2, line 66 to col. 3, line 11). The lower waveguide (10, 12, 14) is composed of a silicon patterned from the single crystal semiconductor material of the device layer of SOI substrate. The lower waveguide (10, 12, 14) are surrounded by shallow trench isolation regions 20 that may be formed by patterning the device layer of the SOI substrate form trenches with lithography and etching, filling the trenches with silicon dioxide and planarizing with chemical mechanical polishing (CMP) (Col. 3, lines 35-56).
The examiner takes OFFICIAL NOTICE that etching method used by Bian for forming trenches in the SOI would necessarily require etch stop layer deposited on a silicon layer of the SOI (Col. 3, lines 35-56).
Bian does not explicitly teach the etch stop layer, patterning the etch stop layer and etching the waveguide layer after the patterning to form a waveguide and a chemical-mechanical polishing (CMP) control structure.
Song teaches forming a stack of layers (Fig. 21 shows SOI 106, oxide layer 108, etch stop layer 1926, and polish stop layer 1022 ),
patterning the etch stop layer (1926, Para [0040]) and etching the waveguide layer with the patterning (Para [0053]-[0057]) to form a waveguide (102A) and a chemical polishing (CMP) control structure (polish stop layer 1022);
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filling a space between the waveguide and the CMP control structure and performing CMP to reduce a thickness of the waveguide, wherein the CMP control structure controls the CMP of the waveguide (1022 functions as a polish stop in the CMP process) to prevent over polishing to an undesired thickness (Para [0053]-[0054]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the step of depositing etch stop layer (1926) to an SOI structure for forming waveguide (102A) would have been modifiable to the manufacturing steps of Bian since Bian teaches forming the trenches with lithography and etching; which implies an etch stop layer. Moreover, depositing the CMP control structure (1022) would have been obvious to one having ordinary skill before the effective filing date of the claimed invention since the CMP control structure is merely a layer of silicon nitride and would have been obvious to adapt in the CMP process of Bian. One motivation for depositing an etch stop layer is to form the waveguide having the CMP control structure as taught by Song so that the planarizing step of CMP would not over polish the waveguide layer.
However, Bian in view of Song do not teach the CMP control structure controls the CMP of the waveguide to form a transitional portion of the waveguide having a gradually changing thickness.
Oxland teaches a CMP process wherein polish stop pillar (502, 508) have different heights to control the gradually changing thickness of the planarized surface. Oxland also teaches filling removing dummy layer 112 and replacing the gate layer 112 with a dielectric.
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It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the varying height polishing stop pillar (502, 508) would be modifiable to the polish stop (1022) of Song for forming tapering waveguides which may require tapering in the height direction. One motivation for modifying single height polish stop with varying height polish stop is to control the height contour of the surface.
Claim 19. Bian / Song / Oxland teach the invention of claim 17, and Song further teaches the etch stop layer comprises silicon nitride (Para [0059]).
Claim 20. Bian / Song / Oxland teach the invention of claim 17, and Bian further teaches wherein the filling of the spaces between the silicon waveguide and the first and second CMP control structures comprises performing a shallow trench isolation (STI) process to fill the spaces between the silicon waveguide and the first and second CMP control structures (Col. 3, lines 35-56).
Claim 22. Bian / Song / Oxland teach the invention of claim 1, and Song further teaches after depositing a layer of the high refractive index material (518), performing a planarizing CMP (Song: Fig. 14-16). It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to one having ordinary skill in the art to replace the high refractive index material (518) of Song with dielectric layer (22) as shown in Bian’s tapered waveguide, and perform CMP to planarize the surface. One would be motivated to replace the high refractive index material (518) with the dielectric layer (22) to form a cladding layer for maintaining the guided light within the waveguide core.
Claim 23. Bian / Song / Oxland teach the invention of claim 22, and Song further teaches the practice steps as disclosed can be performed in different order or not performed depending on specific applications (Para [0037], [0049], [0057]). It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize CMP planarizing can be performed on any layers of substrate that would require a planarized surface to receive the next processing step there.
Claims 2, 18, and 24-26 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Bian / Song / Oxland as applied to claim 1 above, and further in view of Doerre et al. (US 5,334,281, herein “Doerre”).
Regarding claim 2, Bian / Song / Oxland teach the invention of claim 1, but Bian / Song / Oxland do not teach:
a first CMP control structure disposed along a first side of the waveguide and spaced apart from the waveguide by spacing that gradually changes over a portion of the first CMP control structure disposed along the transitional portion of the waveguide; and
a second CMP control structure disposed along a second side of the waveguide opposite the first side of the waveguide and spaced apart from the waveguide by a spacing that gradually changes over a portion of the second CMP control structure disposed along the transitional portion of the waveguide;
wherein the gradually changing spacings of the first and second CMP control structures disposed along the transitional portion of the waveguide controls the CMP of the waveguide to produce the gradually changing thickness of the transitional portion of the waveguide.
Doerre teaches depositing a silicon nitride (“nitride 47”) layer as a polish stop for planarizing substrate. Doerre teaches the minimum width for the use of a polish stop layers will be comparable to twice the polish height adjustment distance. This distance between the polish stop layers is referred to as the “polish height adjustment distance” (Col. 4, line 35). The polish height adjustment distance will depend on the stiffness of the tool and the distance between the polish stop layers. A softer polish tool would reach a greater depth when the polish stop layers are close together. Therefore, by adjusting the distance between the polish stop layers and the stiffness of the polish tool, one having ordinary skill in the art would be able to control the gradual changing thickness of the polishing region (Col. 4, lines 1-49).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the teaching of Doerre’s polish height adjustment distance would be modifiable to the varying height polish stops of Bian / Song / Oxland (Oxland Fig. 5). One would modify the polish stops (502, 508) of Bian / Song / Oxland by providing lateral polish stops having varying widths to adjust for the polish height adjustment and in the art of tapered waveguide controlling the tapering directions (x, y, z in the Cartesian coordinate system) would allow improved coupling efficiencies.
Claim 18. Bian / Song / Oxland teach the invention of claim 17. Song further teaches a spacing between the first CMP control structure (1022 on the right in Fig. 12) and the silicon waveguide (102A) and a spacing between the CMP control structure (1022, not labeled, on the left in Fig. 12) and silicon waveguide (102A).
However, Bian / Song / Oxland do not explicitly teach gradual change in the spacing between the first CMP control structure and the silicon waveguide (102A) along the transitional portion of the waveguide and the gradual change in the spacing between the second CMP control structure and the silicon waveguide (102A) along the transitional portion of the waveguide.
Doerre teaches depositing a silicon nitride (“nitride 47”) layer as a polish stop for planarizing substrate. Doerre teaches the minimum width for the use of a polish stop layers will be comparable to twice the polish height adjustment distance. This distance between the polish stop layers is referred to as the “polish height adjustment distance” (Col. 4, line 35). The polish height adjustment distance will depend on the stiffness of the tool and the distance between the polish stop layers. A softer polish tool would reach a greater depth when the polish stop layers are close together. Therefore, by adjusting the distance between the polish stop layers and the stiffness of the polish tool, one having ordinary skill in the art would be able to control the gradual changing thickness of the polishing region (Col. 4, lines 1-49).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the teaching of Doerre’s polish height adjustment distance would be modifiable polish stops (1022) of Bian / Song / Oxland (Oxland Fig. 5) to vary the polish height adjustment distance of the waveguide (102A). The result of the modification would necessarily yield the gradual changing spacing of the first CMP control structure 1022) and the gradually changing spacing of the second CMP control structure controls the CMP of the silicon waveguide to produce the gradually changing thickness of the transitional portion of the silicon waveguide as taught by Bian / Song / Oxland by providing lateral polish stops (1022) having varying widths to adjust for the polish height adjustment and in the art of tapered waveguide controlling the tapering directions (x, y, z in the Cartesian coordinate system) would allow improved coupling efficiency.
Regarding claim 24, Bian / Song / Oxland in view of Doerre teach the invention of claim 2, and Song further teaches silicon layer on SOI can be removed to expose the buried oxide layer forming the lower cladding for the silicon layer (Para [0039], and Song also teaches the etch stop layer is silicon nitride (Para [0059]).
Regarding claim 25, Bian discloses a waveguide fabrication method comprising:
forming a stack of layers (SOI substrate includes silicon layer and buried oxide layer 16) wherein waveguides (10, 12, 14) are arranged on a buried oxide (BOX) layer 16 of the SOI substrate, the BOX layer 15 operates as a lower cladding providing confinement for the lower waveguides (10, 12, 14) (Col. 2, line 66 to col. 3, line 11). The lower waveguide (10, 12, 14) is composed of a silicon patterned from the single crystal semiconductor material of the device layer of SOI substrate. The lower waveguide (10, 12, 14) are surrounded by shallow trench isolation regions 20 that may be formed by patterning the device layer of the SOI substrate form trenches with lithography and etching, filling the trenches with silicon dioxide and planarizing with chemical mechanical polishing (CMP) (Col. 3, lines 35-56).
Bian does not explicitly teach the etch stop layer, patterning the etch stop layer and etching the waveguide layer after the patterning to form a waveguide and a chemical-mechanical polishing (CMP) control structure.
Song teaches forming a stack of layers (Fig. 21 shows SOI 106, oxide layer 108, etch stop layer 1926, and polish stop layer 1022 ),
patterning the etch stop layer (1926, Para [0040]) and etching the waveguide layer with the patterning (Para [0053]-[0057]) to form a waveguide (102A) and a chemical polishing (CMP) control structure (polish stop layer 1022);
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filling a space between the waveguide and the CMP control structure and performing CMP to reduce a thickness of the waveguide, wherein the CMP control structure controls the CMP of the waveguide (1022 functions as a polish stop in the CMP process) to prevent over polishing to an undesired thickness (Para [0053]-[0054]).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the step of depositing etch stop layer (1926) to an SOI structure for forming waveguide (102A) would have been modifiable to the manufacturing steps of Bian since Bian teaches forming the trenches with lithography and etching; which implies an etch stop layer. Moreover, depositing the CMP control structure (1022) would have been obvious to one having ordinary skill before the effective filing date of the claimed invention since the CMP control structure is merely a layer of silicon nitride and would have been obvious to adapt in the CMP process of Bian. One motivation for depositing an etch stop layer is to form the waveguide having the CMP control structure as taught by Song so that the planarizing step of CMP would not over polish the waveguide layer.
However, Bian in view of Song do not teach the CMP control structure controls the CMP of the waveguide to form a transitional portion of the waveguide having a gradually changing thickness.
Oxland teaches a CMP process wherein polish stop pillar (502, 508) have different heights to control the gradually changing thickness of the planarized surface. Oxland also teaches filling removing dummy layer 112 and replacing the gate layer 112 with a dielectric.
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It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the varying height polishing stop pillar (502, 508) would be modifiable to the polish stop (1022) of Song for forming tapering waveguides which may require tapering in the height direction. One motivation for modifying single height polish stop with varying height polish stop is to control the height contour of the surface.
However, Bian / Song / Oxland do not explicitly teach gradual change in the spacing between the first CMP control structure and the silicon waveguide (102A) along the transitional portion of the waveguide and the gradual change in the spacing between the second CMP control structure and the silicon waveguide (102A) along the transitional portion of the waveguide.
Doerre teaches depositing a silicon nitride (“nitride 47”) layer as a polish stop for planarizing substrate. Doerre teaches the minimum width for the use of a polish stop layers will be comparable to twice the polish height adjustment distance. This distance between the polish stop layers is referred to as the “polish height adjustment distance” (Col. 4, line 35). The polish height adjustment distance will depend on the stiffness of the tool and the distance between the polish stop layers. A softer polish tool would reach a greater depth when the polish stop layers are close together. Therefore, by adjusting the distance between the polish stop layers and the stiffness of the polish tool, one having ordinary skill in the art would be able to control the gradual changing thickness of the polishing region (Col. 4, lines 1-49).
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the teaching of Doerre’s polish height adjustment distance would be modifiable polish stops (1022) of Bian / Song / Oxland (Oxland Fig. 5) to vary the polish height adjustment distance of the waveguide (102A). The result of the modification would necessarily yield the gradual changing spacing of the first CMP control structure 1022) and the gradually changing spacing of the second CMP control structure controls the CMP of the silicon waveguide to produce the gradually changing thickness of the transitional portion of the silicon waveguide as taught by Bian / Song / Oxland by providing lateral polish stops (1022) having varying widths to adjust for the polish height adjustment and in the art of tapered waveguide controlling the tapering directions (x, y, z in the Cartesian coordinate system) would allow improved coupling efficiencies.
Regarding claim 26, Bian / Song / Oxland in view of Doerre teach the invention of claim 25, and Song further teaches the first CMP control structure, and the second CMP control structure each comprises silicon, and the cladding material comprises silicon dioxide since Song’s modification of Bian by depositing the CMP control layer (1022) and etch through the SOI of Bian, the resulting layers would have buried oxide cladding material and silicon material of the top surface of the SOI layer.
Claims 8 and 21 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Bian / Song / Oxland as applied to claim 7 above, and further in view of Yokoyama et al. (JP 2000216492 A, herein “Yokoyama”).
Bian / Song / Oxland teach the invention of claim 7, but Bian / Song / Oxland do not teach disposing a light emitter at an input end of the first portion of the waveguide wherein the input end is distal from the transitional portion of the waveguide; or. disposing a light detector at an output end of the main portion of the waveguide wherein the input end is distal from the transitional portion of the waveguide.
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Yokoyama teaches a semiconductor laser (1) integrated with a spot size converter waveguide (38). The input end is distal from the transitional portion of the waveguide.
It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize the tapered waveguide is a mode or spot size converter, expanding the spot or reducing the spot size. One having skilled in the art would recognize the motivation of coupling efficiency to transform the spot size from an emitter to a source such as optical fiber.
Regarding claim 21, Bian / Song / Oxland in view of Yokoyama teach a light emitter is coupled to the waveguide wherein the input end is distal from the transitional portion of the waveguide. However, Bian / Song / Oxland in view of Yokoyama do not teach disposing a light detector at an output end of the main portion of the waveguide. It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to recognize coupling light into the waveguide from a light emitter, as known to the inventors Bian / Song / Oxland in view of Yokoyama, the inventors would have known to couple light from the waveguide to a light detector. One having skilled in the art would recognize the motivation of coupling efficiency to transform the spot size to couple to a light detector.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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