DETAILED ACTION
1. This Office action is in response to the amendment filed on 09/22/2026.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claim(s) 21 - 22 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Kawagishi (JP 2009/065819 A) in view of Sugie (US Pub. No. 2023/0268829 A1); (hereinafter Kawagishi and Sugie), both cited in previous office action dated 07/23/2026.
Regarding claim 21, Kawagishi [e.g., Fig. 6] discloses a device [e.g., -- FIG. 6 is a configuration diagram of a charge pump circuit showing a second embodiment --], comprising: a charge pump [e.g., diode 14, capacitors 13 and 15 and buffer 16] configured to generate an output voltage signal [e.g., output voltage at node N13] based on a first voltage signal [e.g., VDD signal] and a second voltage signal [e.g., voltage V11 at node N11]; a regulator [e.g., voltage/current converter 60] configured to adjust the second voltage signal to a first voltage level [e.g., adjusts voltage V11 on node N11 to level of VDD] according to the first voltage signal and a third voltage signal [e.g., according to VDD voltage signals and feedback voltage V30]; and a controller [e.g., differential amplifier 30 and reference voltage generator 40] configured to control the third voltage signal [e.g., controls V30] according to the first voltage signal [e.g., according to VDD supplied to N13] and a fourth voltage signal [e.g., VREF via non-inverting terminal of OP 33], wherein the output voltage signal has a second voltage level [e.g., level of output voltage], the fourth voltage signal has a third voltage level [e.g., voltage level of VREF], the third voltage level is approximately equal to one-Nth of the second voltage level, for N being a positive integer [e.g., voltage level of VREF proportional to output voltage level OUT, p. 0023-0024 recites "As a result, the output voltage OUT is represented by the following equation when the hysteresis width VHY is O, assuming that the resistance values of the resistors 31 and 32 are R31 and R32, respectively. OUT = REF X (R31 + R32) / R32, Therefore, an arbitrary output voltage OUT can be obtained by appropriately setting the reference voltage REF, the resistance values R31 and R32, and the hysteresis width VHY."], the regulator comprises a first amplifier [e.g., error amplifier 61] configured to receive each of the second voltage signal [e.g., receives signal corresponding to V11 via inverting input terminal, p. 0033 recites "Further, the voltage-current converter 60 has an NMOS 64 whose source is connected to the power supply voltage VDD and whose gate is connected to the output terminal of the operational amplifier 61, SO that a current proportional to the current flowing in the NMOS 62 flows. The drain of the NMOS 62 is connected to the node N11 via the NMOS 65 for switching."] and the third voltage signal [e.g., voltage V30 signal generated by differential amplifier 30 and reference voltage circuit 40],
Kawagishi does not disclose the controller comprises a first switch, a first terminal of the first switch configured to receive the first voltage signal, and a second terminal of the first switch configured to provide the third voltage signal.
Sugie [e.g., Fig. 4] teaches the controller [e.g., charge pump 120A with integral control CP CTRL 122 and Driver 124] comprises a first switch [e.g., M31], a first terminal of the first switch configured to receive the first voltage signal [e.g., M31 receiving VCC], and a second terminal of the first switch configured to provide the third voltage signal [e.g., second terminal of M31 generating output voltage].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kawagishi with the controller comprises a first switch, a first terminal of the first switch configured to receive the first voltage signal, and a second terminal of the first switch configured to provide the third voltage signal as suggested by Sugie to alternately apply the input voltage and a ground voltage to a node in response to the clock signal.
Regarding claim 22, Kawagishi [e.g., Fig. 6] discloses a second switch [e.g., NMOS 64], wherein a first terminal of the second switch is configured to receive the first voltage signal [e.g., bottom terminal (drain) of NMOS 64 connected to the node N11 via the NMOS 65 for switching], and a control terminal of the second switch is coupled to an output terminal of the first amplifier [e.g., gate of NMOS 64 connected to output of operation amplifier OP 61].
Regarding claim 26, Kawagishi discloses the claimed invention except for a second switch, a first terminal of the second switch configured to receive the first voltage signal, and a second terminal of the second switch configured to provide the third voltage signal.
Sugie [e.g., Fig. 4] teaches a second switch [e.g., M32], a first terminal of the second switch configured to receive the first voltage signal [e.g., M32 receiving VCC via M31], and a second terminal of the second switch configured to provide the third voltage signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kawagishi with a second switch, a first terminal of the second switch configured to receive the first voltage signal, and a second terminal of the second switch configured to provide the third voltage signal as suggested by Sugie to alternately apply the input voltage and a ground voltage to a node in response to the clock signal.
7. Claim(s) 23 - 24 are rejected under 35 U.S.C. 103 as being unpatentable over Kawagishi (JP 2009/065819 A_Fig. 6) in view of Sugie (US Pub. No. 2023/0268829 A1) and Kawagishi (JP 2009/065819 A_Fig. 1); (hereinafter Kawagishi_Fig. 6, Sugie and Kawagishi_Fig. 1), all cited in previous office action dated 07/23/2026.
Regarding claim 23, Kawagishi_Fig. 6 [e.g., Fig. 6] discloses wherein the charge pump comprises: a first diode configured to receive the second voltage signal [e.g., diode 14].
Kawagishi_Fig. 6 does not disclose a second diode coupled to an output terminal of the first diode, and configured to output the output voltage signal.
Kawagishi_Fig. 1 teaches a second diode coupled to an output terminal of the first diode [e.g., diode 14 connected to output of diode 11], and configured to output the output voltage signal [e.g., configured to generate output voltage].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kawagishi_Fig. 6 with a second diode coupled to an output terminal of the first diode, and configured to output the output voltage signal as suggested by Kawagishi_Fig. 1 to control/restrict the flow of current as the capacitor charges/discharges.
Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kawagishi_Fig. 6 with a second diode coupled to an output terminal of the first diode, and configured to output the output voltage signal as suggested by Kawagishi_Fig. 1 since the background recited in the discloser recognizes that it is known in the art that the configuration of a second diode coupled to an output terminal of the first diode, and configured to output the output voltage signal it's well understood and used in the art [e.g., -- refer to Fig. 2 for configuration of a conventional charge pump circuit --].
Regarding claim 24, Kawagishi [e.g., Fig. 6] discloses wherein the charge pump further comprises: a clock buffer configured to receive the first voltage signal [e.g., buffer 16], wherein an output terminal of the clock buffer is coupled to the first node [e.g., node N11 or N12].
Kawagishi [e.g., Fig. 6] does not disclose a capacitor coupled between the output terminal of the first diode and a first node.
Kawagishi_Fig. 1 teaches a capacitor coupled between the output terminal of the first diode and a first node [e.g., capacitor 13 coupled between the output of diode 11 and node N11].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kawagishi_Fig. 6 with a capacitor coupled between the output terminal of the first diode and a first node as suggested by Kawagishi_Fig. 1 to control the flow of current as the capacitor charges/discharges.
Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kawagishi_Fig. 6 with a capacitor coupled between the output terminal of the first diode and a first node as suggested by Kawagishi_Fig. 1 since the background recited in the discloser recognizes that it's is known in the art that the configuration of wherein the charge pump further comprises: a capacitor coupled between the output terminal of the first diode and a first node it's well understood and used in the art [e.g., -- refer to Fig. 2 for configuration of a conventional charge pump circuit --].
Examiner’s Note
8. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
9. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention
Allowable Subject Matter
10. Claims 10 – 20 are allowed.
11. Claims 27 – 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 10 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… a third switch configured to adjust a voltage level of a first node to the third voltage level according to the first voltage signal, control terminals of the third switch and the plurality of switches being coupled to each other; a first resistor, a first terminal of the first resistor being coupled to the first node; and a fourth switch configured to adjust a voltage level of a second node according to the first voltage signal wherein a second terminal of the first resistor is coupled to the second node.”
Claims 11 - 16 each depend either directly or indirectly, from claim 10 and are therefore allowable for the same reasons.
The primary reason for the indication of the allowability of claim 17 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “… adjusting a first node of the controller to a fifth voltage level by a plurality of switches according to each of the supply voltage signal, the first voltage signal, a first resistor and a second resistor, wherein the third voltage signal has the fifth voltage level, a number of the plurality of switches is M, for M being a positive integer, a resistance of the second resistor is approximately X times a resistance of the first resistor, for X being a positive integer, and M multiplied by X divided by N equals 1.”
Claims 18 - 20 each depend either directly or indirectly, from claim 17 and are therefore allowable for the same reasons.
The primary reason for the indication of the allowability of claim 27 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…wherein the controller further comprises: a second amplifier; and a second switch configured to receive the first voltage signal, wherein an output terminal of the second amplifier being coupled to a control terminal of the first switch, and an input terminal of the second amplifier being coupled to the second switch.”
The primary reason for the indication of the allowability of claim 30 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…wherein the controller further comprises: a second amplifier, an output terminal of the second amplifier being coupled to a control terminal of the first switch, an input terminal of the second amplifier being coupled to a first node; a resistor coupled between the first node and a second node; a third amplifier, an input terminal of the third amplifier being coupled to the second node; and a second switch coupled to the second node and an output terminal of the third amplifier.”
Conclusion
12. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
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