DETAILED ACTION
1. This Office action is in response to the amendment filed on 01/20/2026.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
4. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Charge Pump with a regulator and an adaptive controller.
Claim Objections
5. Claim 10 is objected to because of the following informalities:
Claim 10 line 2 recites “… configured to generate a first voltage signal and a second voltage…”. However, it appears that it should recite “… configured to receive a first voltage signal and a second voltage…”. As shown in Fig. 1, the Charge Pump 110 receives VDIO and VIN as input to generate output voltage at node N11. Additionally, as recited in p. 0015 “the charge pump 110 is configured to generate an output voltage signal VOUT according to a system voltage signal VDIO and an input voltage signal VIN.” For examination purposes, the examiner will interpret claims 1 as “… configured to receive a first voltage signal and a second voltage…” as shown in Fig. 1 and recited in paragraphs 0015.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
7. Claim(s) 10 - 13, 17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Sugie (US Pub. No. 2023/0268829 A1); (hereinafter Sugie).
Regarding claim 10, Sugie [e.g., Fig. 4] discloses a device [e.g., power supply circuit 100A], comprising: a charge pump [e.g., charge pump 120A] configured to receive a first voltage signal [e.g., signal VCC] and a second voltage signal [e.g., signal VREGOUT] to generate an output voltage signal [e.g., Vout]; a regulator [e.g., regulator 110] configured to adjust the second voltage signal to a first voltage level [e.g., adjust VREGOUT to VCC level] according to the first voltage signal and a third voltage signal [e.g., according to VCC and VFB]; and a controller [e.g., CP Control 122 and driver 124] configured to control the third voltage signal according to the first voltage signal and a fourth voltage signal [e.g., controls VFB according to VCC and monitoring voltage VMON], wherein the output voltage signal has a second voltage level [e.g., level of output voltage, p. 0040 recites “The power supply circuit 100 receives an input voltage (power supply voltage) VCC at the input terminal 102 and supplies a stabilized output voltage VOUT to a load connected to the output terminal 104. For example, the output voltage VOUT is about 12V, and the input voltage VCC can be taken between a first voltage (for example, 15V, 24V, or 60V) higher than 12V and a second voltage (for example, 6V) lower than 12V.”], the fourth voltage signal has a third voltage level [e.g., voltage level of VMON corresponding on voltage via voltage divider circuit 106], and the third voltage level is approximately equal to one-Nth of the second voltage level, for N being a positive integer [e.g., monitoring voltage level VMON corresponds to a fraction of the voltage level of the output voltage VOUT via voltage dividing circuit R11 - R13, p. 0074 recites “The monitoring voltage VMON is expressed by the following VMON = VOUT×(R12+R13)/(R11+R12+R13)“].
Regarding claim 11, Sugie [e.g., Fig. 4] discloses a plurality of switches comprising a first switch and a second switch [e.g., Driver 124 comprising M31 and M32], wherein each of first terminals of the plurality of switches is coupled to a first node [e.g., M31 and M32 coupled to node FB via voltage divider circuit 106. For examination purposes, the examiner will interpret the term “coupled” in its broadest sense to refer as electrical components that are connected directly or indirectly in a way that allows for the transfer of electrical energy or signals between them], each of second terminals of the plurality of switches is configured to receive the first voltage signal [e.g., switches M31 and M32 receives VCC, p.0066 recites “The driver circuit 124 is connected to a second input node IN2 and receives an input voltage VCC. The driver circuit 124 alternately applies the input voltage VCC and a ground voltage (0 V) to a first end CPL of the flying capacitor Cf in response to the clock signal CLK. The driver circuit 124 is, for example, an inverter, and includes transistors M31 and M32.”], and the regulator is configured to receive the third voltage signal from the first node [e.g., regulator 110 receiving feedback voltage VFB via voltage divider circuit node 106].
Regarding claim 12, Sugie [e.g., Fig. 4] discloses a third switch [e.g., M22] configured to adjust a voltage level [e.g., voltage level of VREGOUT] of a second node to the third voltage level according to the first voltage signal [e.g., adjust voltage level at node VREGOUT according to VCC]; and a first amplifier [e.g., error amplifier 112] configured to receive the fourth voltage signal [e.g., receives feedback voltage VFB via voltage divider circuit node 106], wherein each of an output terminal of the first amplifier and each of control terminals of the third switch and the plurality of switches is coupled to each other [e.g., output terminal of error amplifier 112 coupled to gate of M22 and gates of M31 and M32 via IN2 node].
Regarding claim 13, Sugie [e.g., Fig. 4] discloses a first resistor [e.g., R11]; and a second resistor coupled to the first node [e.g., R12 coupled to output node VOUT], wherein a first terminal of the first resistor is coupled to the second node [e.g., top terminal of resistor R11 coupled to node IN1 when switches 126 and 128 are conducting].
Regarding claim 17, Sugie [e.g., Figs. 4 and 5] discloses a method, comprising: inputting a first voltage signal [e.g., monitoring voltage signal VMON inputted to CP CTRL 122] and a second voltage signal [e.g., voltage signal VREGOUT] to a controller [e.g., inputted to Charge Pump 120A with Controller CP CTRL 122]; outputting a third voltage signal from the controller [e.g., Charge Pump 120A with Controller CP CTRL 122 output Vout signal] according to the first voltage signal and the second voltage signal [e.g., output voltage signal Vout outputted according on monitoring voltage signal VMON and voltage signal VREGOUT]; and generating a fourth voltage signal [e.g., generating feedback voltage signal VFB via voltage divider circuit 106] according to the third voltage signal [e.g., according to output voltage signal Vout] and a supply voltage signal [e.g., VCC],
wherein a first voltage level of the first voltage signal [e.g., voltage level of monitoring voltage VMON] is approximately equal to one-Nth of a second voltage level of the fourth voltage signal, for N being a positive integer [e.g., monitoring voltage VMON is a fraction of feedback voltage VFB produced by the voltage divider circuit 106, p. 0050 recites “The error amplifier 112 amplifies an error between the feedback voltage VFB and the reference voltage VREF and feedback-controls a gate voltage of the first transistor M21. The feedback voltage VFB is generated by a voltage divider circuit 106 including resistors R11 to R13 and is expressed by the following: VFB = VOUT× R13/(R11+R12+ R13)”. It continues on p. 0074 recites “The first comparator COMP1 is a hysteresis comparator and compares a monitoring voltage VMON corresponding to the output voltage VOUT with an upper threshold VTHH and a lower threshold VTHL corresponding to the second target voltage VOUT(REF2). The monitoring voltage VMON is expressed by the following: VMON=VOUT×(R12+R13)/(R11+R12+R13)”], and a third voltage level of the second voltage signal [e.g., voltage level of VREGOUT] is approximately equal to one-Nth of a fourth voltage level of the supply voltage signal [e.g., -- refer to FIG. 5 is an operation waveform diagram of the power supply circuit 100A of FIG. 4 --, VREGOUT is less than of VCC (proportional to voltage drop across M21].
Regarding claim 19, Sugie [e.g., Figs. 4 and 5] discloses adjusting a first node of the controller to the first voltage level [e.g., adjust output voltage on voltage divider circuit 106 node according to monitoring voltage VMON] by a first switch [e.g., switch M22] and a first amplifier [e.g., error amplifier 112] according to the supply voltage signal and the first voltage signal [e.g., according to reference voltage VREF and monitoring voltage VMON ], wherein a control terminal of the first switch is coupled to an output terminal the first amplifier [e.g., control terminal of M22 coupled to output 112].
8. Claim(s) 21 - 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawagishi (JP 2009/065819 A); (hereinafter Kawagishi).
Regarding claim 21, Kawagishi [e.g., Fig. 6] discloses a device [e.g., -- FIG. 6 is a configuration diagram of a charge pump circuit showing a second embodiment --], comprising: a charge pump [e.g., diode 14, capacitors 13 and 15 and buffer 16] configured to generate an output voltage signal [e.g., output voltage at node N13] based on a first voltage signal [e.g., VDD signal] and a second voltage signal [e.g., voltage V11 at node N11]; a regulator [e.g., voltage/current converter 60] configured to adjust the second voltage signal to a first voltage level [e.g., adjusts voltage V11 on node N11 to level of VDD] according to the first voltage signal and a third voltage signal [e.g., according to VDD voltage signals and feedback voltage V30]; and a controller [e.g., differential amplifier 30 and reference voltage generator 40] configured to control the third voltage signal [e.g., controls V30] according to the first voltage signal [e.g., according to VDD supplied to N13] and a fourth voltage signal [e.g., VREF via non-inverting terminal of OP 33], wherein the output voltage signal has a second voltage level [e.g., level of output voltage], the fourth voltage signal has a third voltage level [e.g., voltage level of VREF], the third voltage level is approximately equal to one-Nth of the second voltage level, for N being a positive integer[e.g., voltage level of VREF proportional to output voltage level OUT , p. 0023-0024 recites “As a result, the output voltage OUT is represented by the following equation when the hysteresis width VHY is 0, assuming that the resistance values of the resistors 31 and 32 are R31 and R32, respectively. OUT = REF × (R31 + R32) / R32, Therefore, an arbitrary output voltage OUT can be obtained by appropriately setting the reference voltage REF, the resistance values R31 and R32, and the hysteresis width VHY.”], the regulator comprises a first amplifier [e.g., error amplifier 61] configured to receive each of the second voltage signal [e.g., receives signal corresponding to V11 via inverting input terminal, p. 0033 recites “Further, the voltage-current converter 60 has an NMOS 64 whose source is connected to the power supply voltage VDD and whose gate is connected to the output terminal of the operational amplifier 61, so that a current proportional to the current flowing in the NMOS 62 flows. The drain of the NMOS 62 is connected to the node N11 via the NMOS 65 for switching.”] and the third voltage signal [e.g., voltage V30 signal generated by differential amplifier 30 and reference voltage circuit 40].
Regarding claim 22, Kawagishi [e.g., Fig. 6] discloses a first switch [e.g., NMOS 64], wherein a first terminal of the first switch is configured to receive the first voltage signal [e.g., bottom terminal (drain) of NMOS 64 connected to the node N11 via the NMOS 65 for switching], and a control terminal of the first switch is coupled to an output terminal of the first amplifier [e.g., gate of NMOS 64 connected to output of operation amplifier OP 61].
Claim Rejections - 35 USC § 103
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claim(s) 23 - 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawagishi (JP 200965819 A_Fig. 6) in view of Kawagishi (JP 200965819 A_Fig. 1); (hereinafter Kawagishi_Fig. 6 and Kawagishi_Fig. 1).
Regarding claim 23, Kawagishi_Fig. 6 [e.g., Fig. 6] discloses wherein the charge pump comprises: a first diode configured to receive the second voltage signal [e.g., diode 14].
Kawagishi_Fig. 6 does not disclose a second diode coupled to an output terminal of the first diode, and configured to output the output voltage signal.
Kawagishi_Fig. 1 teaches a second diode coupled to an output terminal of the first diode [e.g., diode 14 connected to output of diode 11], and configured to output the output voltage signal [e.g., configured to generate output voltage].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kawagishi_Fig. 6 with a second diode coupled to an output terminal of the first diode, and configured to output the output voltage signal as suggested by Kawagishi_Fig. 1 to control the flow of current as the capacitor charges/discharges. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kawagishi_Fig. 6 with a second diode coupled to an output terminal of the first diode, and configured to output the output voltage signal as suggested by Kawagishi_Fig. 1 since the background recited in the discloser recognizes that it is known in the art that the configuration of a second diode coupled to an output terminal of the first diode, and configured to output the output voltage signal it’s well understood and used in the art [e.g., -- refer to Fig. 2 for configuration of a conventional charge pump circuit --].
Regarding claim 24, Kawagishi [e.g., Fig. 6] discloses wherein the charge pump further comprises: a capacitor coupled between the output terminal of the first diode and a first node; and a clock buffer configured to receive the first voltage signal [e.g., buffer 16], wherein an output terminal of the clock buffer is coupled to the first node [e.g., node N11 or N12].
Kawagishi [e.g., Fig. 6] does not discloses a capacitor coupled between the output terminal of the first diode and a first node.
Kawagishi_Fig. 1 teaches a capacitor coupled between the output terminal of the first diode and a first node [e.g., capacitor 13 coupled between the output of diode 11 and node N11].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kawagishi_Fig. 6 with a capacitor coupled between the output terminal of the first diode and a first node as suggested by Kawagishi_Fig. 1 to control the flow of current as the capacitor charges/discharges. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kawagishi_Fig. 6 with a capacitor coupled between the output terminal of the first diode and a first node as suggested by Kawagishi_Fig. 1 since the background recited in the discloser recognizes that it’s is known in the art that the configuration of wherein the charge pump further comprises: a capacitor coupled between the output terminal of the first diode and a first node it’s well understood and used in the art [e.g., -- refer to Fig. 2 for configuration of a conventional charge pump circuit --].
12. Claim(s) 25 - 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawagishi (JP 200965819 A) in view of Sugie (US Pub. No. 2023/0268829 A1); (hereinafter Kawagishi and Sugie).
Regarding claim 25, Kawagishi discloses the claimed invention except for wherein the controller comprises: a first switch, a first terminal of the first switch configured to receive the first voltage signal, and a second terminal of the first switch configured to provide the third voltage signal.
Sugie [e.g., Fig. 4] teaches wherein the controller [e.g., charge pump 120A with integral control CP CTRL 122 and Driver 124] comprises: a first switch [e.g., M31], a first terminal of the first switch configured to receive the first voltage signal [e.g., M31 receiving VCC], and a second terminal of the first switch configured to provide the third voltage signal [e.g., second terminal of M31 generating output voltage].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kawagishi with wherein the controller comprises: a first switch, a first terminal of the first switch configured to receive the first voltage signal, and a second terminal of the first switch configured to provide the third voltage signal as suggested by Sugie to alternately apply the input voltage and a ground voltage to a node in response to the clock signal.
Regarding claim 26, Kawagishi discloses the claimed invention except for a second switch, a first terminal of the second switch configured to receive the first voltage signal, and a second terminal of the second switch configured to provide the third voltage signal.
Sugie [e.g., Fig. 4] teaches a second switch [e.g., M32], a first terminal of the second switch configured to receive the first voltage signal [e.g., M32 receiving VCC via M31], and a second terminal of the second switch configured to provide the third voltage signal.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Kawagishi with a second switch, a first terminal of the second switch configured to receive the first voltage signal, and a second terminal of the second switch configured to provide the third voltage signal as suggested by Sugie to alternately apply the input voltage and a ground voltage to a node in response to the clock signal.
Examiner’s Note
13. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
14. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention
Allowable Subject Matter
15. Claims 14 - 16, 18, 20 and 27 - 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 14 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…a fourth switch configured to adjust a voltage level of a third node to a fourth voltage level according to the first voltage signal, wherein a second terminal of the first resistor is coupled to the third node, the first voltage signal has a fifth voltage level, and the fourth voltage level is approximately equal to one-Nth of the fifth voltage level.”
The primary reason for the indication of the allowability of claim 18 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “…, wherein the third voltage signal has the fifth voltage level, a number of the plurality of switches is M, for M being a positive integer, each of control terminals of the plurality of the switches is coupled to each other, a resistance of the second resistor is approximately X times a resistance of the first resistor, for X being a positive integer, and M multiplied by X divided by N equals 1.”
The primary reason for the indication of the allowability of claim 20 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “adjusting a second node of the controller to the third voltage level by a second switch and a second amplifier according to the supply voltage signal, wherein a control terminal of the second switch is coupled to an output terminal the second amplifier.”
The primary reason for the indication of the allowability of claim 27 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of
“a second amplifier; and a second switch configured to receive the first voltage signal, wherein an output terminal of the second amplifier being coupled to a control terminal of the first switch, and an input terminal of the second amplifier being coupled to the second switch.”
Conclusion
16. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Pub. No. 2015/0270774 A1 (Tamura et al) disclosure relates to a power supply circuit for generating an output voltage having a predetermined target value from an input voltage.
US Pub. No. 2016/0054747 A1 (Cohen et al) discloses an apparatus of a supply generator using dynamic circuit reference.
US Patent No. 6,643,151 B1 (Nebrigic et al) discloses a DC/DC power supply controllers, and more particularly to regulated charge pump power converters for integrated power management systems.
US Pub. No. 2024/0333145 A1 (Meillereux et al) discloses charge pump regulators and integrated circuits containing such regulators.
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ULARISLAO CORDOVA whose telephone number is (571)272-4690. The examiner can normally be reached Monday-Friday 7:30 - 5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/ULARISLAO CORDOVA/Examiner, Art Unit 2838
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