DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8-15, and 17-20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Chang, US 2023/0209836 A1.
Claim 1: Chang discloses
a substrate (37);
a channel layer (89) disposed over the substrate to extend in a vertical direction substantially perpendicular to a surface of the substrate;
an interfacial dielectric layer (69) disposed on the channel layer;
a floating electrode layer (85) disposed on the interfacial dielectric layer, the floating electrode layer including first and second electrode portions respectively disposed on different portions (left and right) of the interfacial dielectric layer;
a ferroelectric layer (83) disposed on the first electrode portion of the floating electrode layer;
a gate electrode (81) layer disposed on the ferroelectric layer;
and an insulation structure (41) covering the second electrode portion of the floating electrode layer over the substrate.
PNG
media_image1.png
346
521
media_image1.png
Greyscale
Claim 2: the channel layer is disposed on an outer circumferential surface of a pillar structure (73) extending in the vertical direction (FIG. 2).
Claim 3: the interfacial dielectric layer is disposed to surround the channel layer along the outer circumferential surface of the pillar structure, and wherein the floating electrode layer is disposed to surround the interfacial dielectric layer along the outer circumferential surface of the pillar structure (FIG. 2).
Claim 4: the first and second electrode portions of the floating electrode layer are electrically connected to each other (they are contiguous).
Claim 5: the ferroelectric layer covers the first electrode portion among the first and second electrode portions of the floating electrode layer (FIG. 2).
Claim 6: Chang discloses
a source line electrode layer (SSG) (404, a layer connected to a source line electrode) disposed between one end portion of the channel layer and the substrate in the vertical direction;
and a bit line electrode layer (BSG) disposed on the other end portion opposite to the one end portion of the channel layer.
Claim 8: an interface area between the first electrode portion of the floating electrode layer and the ferroelectric layer is smaller than an interface area between the interfacial dielectric layer and the first and second electrode portions of the floating electrode layer. The first and second portions can be arbitrarily divided, so for a small first portion, this will be so. Also for a thin floating gate this will be so.
PNG
media_image2.png
346
524
media_image2.png
Greyscale
Here the interface area between the interfacial dielectric layer and the first and second electrode portions of the floating electrode layer goes around the pillar. (Note that the first and second portions have been switched simply to make it easier to show the division between them.)
Claim 9: Chang discloses
a substrate (41);
a channel layer (89) disposed over the substrate to extend in a vertical direction substantially perpendicular to a surface of the substrate;
an interfacial dielectric layer (69) disposed on a sidewall surface of the channel layer along the vertical direction;
a plurality of floating electrode layers (85) disposed over the substrate to be spaced apart from each other along the vertical direction, each of the floating electrode layers including first and second electrode portions (on the left and right sides) disposed on a plane substantially parallel to the surface of the substrate;
a plurality of ferroelectric layers (83) disposed to respectively contact the first electrode portions of the floating electrode layers;
a plurality of gate electrode layers (81) disposed to be adjacent to the plurality of ferroelectric layers;
and an insulation structure (41) covering (top and bottom sides) the second electrode portions of each of the plurality of floating electrode layers over the substrate. See the annotated FIG. 2 above; see FIG. 1 for the multiple layers.
Claim 10: the first and second electrode portions of each of the floating electrode layers are disposed to respectively contact different portions (left and right side) of the interfacial dielectric layer.
Claim 11: the channel layer is disposed on an outer circumferential surface of a pillar structure (73) extending in the vertical direction (FIG. 2).
Claim 12: the interfacial dielectric layer is disposed to surround the channel layer along the outer circumferential surface of the pillar structure, and wherein the plurality of floating electrode layers are disposed to surround the interfacial dielectric layer along the outer circumferential surface of the pillar structure (FIG. 2).
Claim 13: a gate electrode layer, corresponding floating electrode layer, and corresponding ferroelectric layer are all disposed on the plane substantially parallel to the surface of the substrate.
PNG
media_image3.png
350
522
media_image3.png
Greyscale
Claim 14: each of the ferroelectric layers covers the first electrode portion among the first and second electrode portions of each of the plurality of floating electrode layers (FIG. 2).
Claim 15: Lu discloses
a source line electrode layer (SSG) (404, a layer connected to a source line electrode) disposed between one end portion of the channel layer and the substrate in the vertical direction;
and a bit line electrode layer (BSG) disposed on the other end portion opposite to the one end portion of the channel layer.
Claim 17: an interface area between the first electrode portion of each of the plurality of floating electrode layers and each of the ferroelectric layers is smaller than an interface area between the first and second electrode portions of each of the plurality of floating electrode layers and the interfacial dielectric layer. The first and second portions can be arbitrarily divided, so for a small first portion, this will be so. Also for a thin floating gate this will be so.
PNG
media_image2.png
346
524
media_image2.png
Greyscale
Here the interface area between the interfacial dielectric layer and the first and second electrode portions of the floating electrode layer goes around the pillar. (Note that the first and second portions have been switched simply to make it easier to show the division between them.)
Claim 18: Chang discloses
a substrate (37);
and memory cell structures disposed along first and second directions that are substantially parallel to a surface of the substrate (FIG. 3),
wherein each of the memory cell structures includes:
a channel layer (89) disposed over the substrate to extend in a vertical direction substantially perpendicular to a surface of the substrate;
an interfacial dielectric layer (69) disposed on the channel layer;
a floating electrode layer (85) disposed on the interfacial dielectric layer, the floating electrode layer including first and second electrode portions respectively disposed on different portions (left and right) of the interfacial dielectric layer;
a ferroelectric layer (83) disposed on the first electrode portion of the floating electrode layer on a (horizontal) plane;
a gate electrode (81) layer disposed on the ferroelectric layer;
and an insulation structure (41) covering the second electrode portion of the floating electrode layer over the substrate.
PNG
media_image1.png
346
521
media_image1.png
Greyscale
Claim 19: Chang discloses a device isolation structure (16, FIGS. 8 and 9) disposed over the substrate to extend in the first direction and to separate neighboring memory cell structures in the second direction.
Claim 20: an interface area between the first electrode portion of the floating electrode layer and the ferroelectric layer is smaller than an interface area between the first and second electrode portions of the floating electrode layer and the interfacial dielectric layer. The first and second portions can be arbitrarily divided, so for a small first portion, this will be so. Also for a thin floating gate this will be so.
PNG
media_image2.png
346
524
media_image2.png
Greyscale
Here the interface area between the interfacial dielectric layer and the first and second electrode portions of the floating electrode layer goes around the pillar. (Note that the first and second portions have been switched simply to make it easier to show the division between them.)
Allowable Subject Matter
Claims 7 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Chang does not disclose that the insulation structure extends vertically to contact the second electrode portions of the plurality of floating electrode layers, the plurality of ferroelectric layers, and the plurality of gate electrode layers, nor could the examiner find a reason that this would have been obvious.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure, showing potentially relevant ferroelectric structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PETER BRADFORD/Primary Examiner, Art Unit 2897
Prosecution Insights